1987 commits

Author	SHA1	Message	Date
Emil J	1b25e1cee0	Merge pull request #4942 from Anhijkt/fix-ice40dsp ... ice40_dsp: fix log_assert issue	2025-03-28 13:32:17 +01:00
Emil J	b2816b22c5	Merge pull request #4965 from YosysHQ/krys/gen_err_files ... More *.err files in test failures	2025-03-28 13:08:44 +01:00
Emil J	ec8b745929	Merge pull request #4733 from antmicro/fix-setundef-pass-for-params ... Fix setting bits of parameters in setundef pass	2025-03-28 13:06:04 +01:00
KrystalDelusion	5b6b3d01bf	Update gen-tests-makefile.sh ... Keep file extensions so that e.g. tribuf.ys and tribuf.sh don't try to output to the same log file.	2025-03-27 10:33:51 +13:00
KrystalDelusion	8a68ae6023	Update gen-tests-makefile.sh	2025-03-27 10:10:49 +13:00
Anhijkt	cb03a1ec21	ice40_dsp: fix test	2025-03-26 15:13:05 +02:00
Scott Ashcroft	518986d45c	Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed	2025-03-25 13:12:04 +00:00
KrystalDelusion	a647731812	Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing ... opt_merge: hashing performance and correctness	2025-03-25 10:36:02 +13:00
Emil J. Tywoniak	980a0a15c1	stat: allow gzipped liberty files	2025-03-19 13:43:44 +01:00
Anhijkt	5ae32efca5	ice40_dsp: add test	2025-03-15 20:05:57 +02:00
KrystalDelusion	9f1271bee0	Merge pull request #4922 from Anhijkt/fix-splitcells-assert ... splitcells: Fix the assertion bug caused by out-of-bound offset	2025-03-14 16:52:38 +13:00
Martin Povišer	6da543a61a	Merge pull request #4818 from povik/macc_v2 ... Add `$macc_v2`	2025-03-12 22:55:40 +01:00
Anhijkt	be3dfdc5ad	splitcells: add tests	2025-03-10 19:41:22 +02:00
Martin Povišer	d8a4991289	Merge pull request #4931 from povik/buf-clean ... opt_clean, simplemap: Add `$buf` handling	2025-03-10 15:10:17 +01:00
Emil J. Tywoniak	33bfc9d19c	opt_merge: test more kinds of cells	2025-03-10 13:14:06 +01:00
Emil J. Tywoniak	ae7a97cc2d	opt_merge: test some unary cells	2025-03-10 13:14:06 +01:00
Emil J. Tywoniak	176faae7c9	opt_merge: fix trivial binary regression	2025-03-10 13:14:06 +01:00
Martin Povišer	557047fe1e	opt_clean, simplemap: Add $buf handling	2025-03-07 16:08:38 +01:00
N. Engelhardt	268a034b21	Merge pull request #4866 from YosysHQ/ql_ioff ... add IOFF inference for qlf_k6n10f	2025-03-03 14:12:09 +00:00
Emil J	b4a169527d	Merge pull request #4894 from YosysHQ/emil/abstract ... Add `abstract` pass for formal verification	2025-02-25 11:16:37 +01:00
Emil J. Tywoniak	3f60a2cc67	abstract: test -slice from:to for -init	2025-02-25 00:22:14 +01:00
Emil J. Tywoniak	3cb7054e53	abstract: test -slice for all modes, -rtlilslice for -init	2025-02-25 00:18:16 +01:00
Emil J. Tywoniak	5bd18613bb	abstract: test -init	2025-02-19 23:03:43 +01:00
Emil J. Tywoniak	34e3fcbb31	abstract: test -value	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	d3a90021ad	abstract: test -state	2025-02-18 17:08:45 +01:00
Jannis Harder	7cd822b7f5	rtlil: Add {from,to}_hdl_index methods to Wire ... In the past we had the occasional bug due to some place not handling all 4 combinations of upto/downto and zero/nonzero start_offset correctly.	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	387d0de383	abstract: -state allow partial abstraction, don't use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	6027030215	abstract: -value MVP, use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	4637fa74e3	abstract: -init MVP	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	e4ca7b8846	abstract: -state MVP	2025-02-18 17:08:45 +01:00
Krystine Sherwin	db5b76edc1	Add test for shifting by INT_MAX ... Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.	2025-02-14 14:01:27 +13:00
N. Engelhardt	303a386ecc	create duplicate IOFFs if multiple output ports are connected to the same register	2025-01-31 11:28:57 +01:00
Jannis Harder	40c690b030	extract_fa: Add test case	2025-01-30 18:45:06 +01:00
N. Engelhardt	9da4fe747e	fix bus ioff inference	2025-01-28 11:23:36 +01:00
Martin Povišer	916fe998ab	macc_v2: Add test	2025-01-27 13:19:26 +01:00
N. Engelhardt	2241a65f78	fix tests not expecting ioffs	2025-01-24 21:29:10 +01:00
N. Engelhardt	1cf8e7c7db	add ioff inference for qlf_k6n10f	2025-01-24 21:17:15 +01:00
Martin Povišer	c5fd96ebb0	macc_v2: Start new cell	2025-01-24 12:38:03 +01:00
N. Engelhardt	7e3990b681	Merge pull request #4837 from YosysHQ/json_scopinfo_opt ... write_json: add option to include $scopeinfo cells	2025-01-10 09:57:22 +00:00
N. Engelhardt	77b28442a5	emit $scopeinfo cells by default	2025-01-08 14:47:46 +01:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
N. Engelhardt	dab7905cbe	write_json: add option to include $scopeinfo cells	2025-01-08 13:33:56 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Emil J	6ab5be4a0e	Merge pull request #4814 from YosysHQ/emil/make-test-fasterer ... test: every test everywhere all at once	2024-12-18 19:02:39 +01:00
Martin Povišer	08778917db	wreduce: Optimize signedness when possible	2024-12-16 12:57:08 +01:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
Emil J. Tywoniak	603e5eb30a	test: every test everywhere all at once	2024-12-12 01:28:36 +01:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00