mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 17:45:33 +00:00
Code Activity

ice40_dsp: fix test

Browse source
This commit is contained in:
Anhijkt 2025-03-26 15:13:05 +02:00
parent a9d765e11e
commit cb03a1ec21
1 changed files with 8 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

13
tests/various/bug4865.ys
View file

@ -1,5 +1,6 @@
read_rtlil << EOF
autoidx 524
attribute \top 1
@ -10,8 +11,10 @@ module \main
attribute \force_downto 1
wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
wire width 14 $delete_wire$514
wire width 12 $delete_wire$514
wire width 4 $test
attribute \module_not_derived 1
cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
parameter \A_REG 1'0
@ -36,7 +39,7 @@ module \main
parameter \TOP_8x8_MULT_REG 1'0
connect \A 16'x
connect \B 16'x
connect \O { $delete_wire$514 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:2] 2'x}
connect \O { $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
@ -46,17 +49,17 @@ module \main
parameter \B_WIDTH 2
parameter \Y_WIDTH 19
connect \A 18'x
connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:16]
connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
connect \Y 19'x
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
parameter \A_SIGNED 0
parameter \A_WIDTH 14
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A $delete_wire$514
connect \A $delete_wire$514 [1:0]
connect \B 2'x
connect \Y 2'x
end