fix bus ioff inference

tests/arch/quicklogic/qlf_k6n10f/ioff.ys

@@ -9,6 +9,18 @@ EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 1 t:dff
 
+design -reset
+# test: acceptable for output IOFF promotion
+read_verilog <<EOF
+module top (input clk, input [3:0] a, output reg [3:0] o);
+    always @(posedge clk) begin
+        o <= ~a;
+    end
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 4 t:dff
+
 design -reset
 # test: acceptable for input IOFF promotion
 read_verilog <<EOF
@@ -23,6 +35,20 @@ EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 1 t:dff
 
+design -reset
+# test: acceptable for input IOFF promotion
+read_verilog <<EOF
+module top (input clk, input [3:0] a, output [3:0] o);
+    reg [3:0] r;
+    always @(posedge clk) begin
+        r <= a;
+    end
+    assign o = ~r;
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 4 t:dff
+
 design -reset
 # test: acceptable for either IOFF promotion
 read_verilog <<EOF
@@ -47,6 +73,18 @@ EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 0 t:dff
 
+design -reset
+# test: not acceptable for output IOFF promotion: output signal is used
+read_verilog <<EOF
+module top (input clk, input [3:0] a, output reg [3:0] o);
+    always @(posedge clk) begin
+        o <= ~a | o;
+    end
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 0 t:dff
+
 design -reset
 # test: not acceptable for input IOFF promotion: input signal is used
 read_verilog <<EOF
@@ -62,6 +100,21 @@ EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 0 t:dff
 
+design -reset
+# test: not acceptable for input IOFF promotion: input signal is used
+read_verilog <<EOF
+module top (input clk, input [3:0] a, output [3:0] o, output [3:0] p);
+    reg [3:0] r;
+    always @(posedge clk) begin
+        r <= a;
+    end
+    assign o = ~r;
+    assign p = ~a;
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 0 t:dff
+
 design -reset
 # test: not acceptable for IOFF promotion: FF has reset
 read_verilog <<EOF
@@ -77,6 +130,21 @@ EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 0 t:dff
 
+design -reset
+# test: not acceptable for IOFF promotion: FF has reset
+read_verilog <<EOF
+module top (input clk, input rst, input [3:0] a, output reg [3:0] o);
+    always @(posedge clk) begin
+        if (rst)
+            o <= 4'b0;
+        else
+            o <= a;
+    end
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 0 t:dff
+
 design -reset
 # test: not acceptable for IOFF promotion: FF has enable
 read_verilog <<EOF
@@ -89,3 +157,16 @@ endmodule
 EOF
 synth_quicklogic -family qlf_k6n10f -top top
 select -assert-count 0 t:dff
+
+design -reset
+# test: not acceptable for IOFF promotion: FF has enable
+read_verilog <<EOF
+module top (input clk, input en, input [3:0] a, output reg [3:0] o);
+    always @(posedge clk) begin
+        if (en)
+            o <= a;
+    end
+endmodule
+EOF
+synth_quicklogic -family qlf_k6n10f -top top
+select -assert-count 0 t:dff