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Merge pull request #4942 from Anhijkt/fix-ice40dsp

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ice40_dsp: fix log_assert issue
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Emil J 2025-03-28 13:32:17 +01:00 committed by GitHub
parent b2816b22c5 cb03a1ec21
commit 1b25e1cee0
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GPG key ID: B5690EEEBB952194
2 changed files with 83 additions and 6 deletions
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19
techlibs/ice40/ice40_dsp.pmg
View file

@ -46,17 +46,24 @@ code sigA sigB sigH
// Only care about those bits that are used
int i;
for (i = 0; i < GetSize(O); i++) {
if (nusers(O[i]) <= 1)
break;
sigH.append(O[i]);
}
for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
;
// This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example
if (i == 0)
reject;
log_assert(nusers(O.extract_end(i)) <= 1);
for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0)
wire_width++;
else {
if (wire_width) { // add empty wires for bit offset if needed
sigH.append(module->addWire(NEW_ID, wire_width));
wire_width = 0;
}
sigH.append(O[j]);
}
endcode
code argQ ffA sigA clock clock_pol

70
tests/various/bug4865.ys Normal file
View file

@ -0,0 +1,70 @@
read_rtlil << EOF
autoidx 524
attribute \top 1
attribute \library "work"
attribute \hdlname "main"
module \main
attribute \force_downto 1
wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
wire width 12 $delete_wire$514
wire width 4 $test
attribute \module_not_derived 1
cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
parameter \A_REG 1'0
parameter \A_SIGNED 0
parameter \BOTADDSUB_CARRYSELECT 2'00
parameter \BOTADDSUB_LOWERINPUT 2'00
parameter \BOTADDSUB_UPPERINPUT 1'0
parameter \BOTOUTPUT_SELECT 2'11
parameter \BOT_8x8_MULT_REG 1'0
parameter \B_REG 1'0
parameter signed \B_SIGNED 0
parameter \C_REG 1'0
parameter \D_REG 1'0
parameter \MODE_8x8 1'0
parameter \NEG_TRIGGER 1'0
parameter \PIPELINE_16x16_MULT_REG1 1'0
parameter \PIPELINE_16x16_MULT_REG2 1'0
parameter \TOPADDSUB_CARRYSELECT 2'00
parameter \TOPADDSUB_LOWERINPUT 2'00
parameter \TOPADDSUB_UPPERINPUT 1'0
parameter \TOPOUTPUT_SELECT 2'11
parameter \TOP_8x8_MULT_REG 1'0
connect \A 16'x
connect \B 16'x
connect \O { $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
parameter \A_SIGNED 0
parameter \A_WIDTH 18
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 19
connect \A 18'x
connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
connect \Y 19'x
end
cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A $delete_wire$514 [1:0]
connect \B 2'x
connect \Y 2'x
end
end
EOF
ice40_dsp