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Code Activity
11608 commits 122 branches 59 tags 72 MiB
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1534 commits

Author SHA1 Message Date
Marcelina Kościelnicka
32d2cc8c28 clkbufmap: improve input pad handling. 
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
 2020-07-09 18:48:01 +02:00
clairexen
802671b22e
Merge pull request #2244 from antmicro/logic 
Add logic type support to parameters
 2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka
03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
 2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717 dfflegalize: Add special support for const-D latches. 
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
 2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka
c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Kamil Rakoczy
b422f2e4d0 Add logic param and integer bad syntax tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-06 09:18:48 +02:00
Dan Ravensloft
09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft
7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Dan Ravensloft
0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka
7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Dan Ravensloft
b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07 tests: update fsm.ys resource count 
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
 2020-07-04 19:45:10 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize 
Add dfflegalize pass.
 2020-07-02 17:46:11 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
Marcelina Kościelnicka
6b42819a37 dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
Zachary Snow
27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Kamil Rakoczy
76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
Kamil Rakoczy
39c39848a2 Add sub-assign and and-assign tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:32:05 +02:00
Kamil Rakoczy
470df03f3d Move combined assign tests to single file 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:19:16 +02:00
Kamil Rakoczy
f6d06c9f7b Add xor-assignment test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 14:46:21 +02:00
Kamil Rakoczy
a5ca4eeefb Add or-assignment and plus-assignment tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:56:26 +02:00
Marcelina Kościelnicka
88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Kazuki Sakamoto
6bf75be73b static cast: add tests 2020-06-19 17:40:38 -07:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
diego
d68a8f9e2b Removing trailing whitespace 2020-06-10 10:35:40 -05:00
Claire Wolf
b3b515087d Fix tests/opt/opt_rmdff 
This only passed before because "prep" was also running opt_rmdff

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 22:48:26 +02:00
diego
3c2a1171ff Adding latch tests for shift&mask AST dynamic part-select enhancements 2020-06-09 15:17:01 -05:00
Peter Crozier
01ec681373 Support 2D bit arrays in structures. Optimise array indexing. 2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00
Claire Wolf
7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung
8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
Miodrag Milanovic
0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Eddie Hung
ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
Eddie Hung
d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
Xiretza
6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Eddie Hung
1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00