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Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes

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abc9: fixes around handling combinatorial loops
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Eddie Hung 2020-06-03 17:35:46 -07:00 • committed by GitHub
commit 45cd323055
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3 changed files with 18 additions and 3 deletions
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tests/arch/ecp5/latches_abc9.ys Normal file
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read_verilog <<EOT
module top(input e, d, output q);
reg l;
always @*
if (e)
l = ~d;
assign q = ~l;
endmodule
EOT
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9
select -assert-count 2 t:LUT4
select -assert-none t:LUT4 %% t:* %D