Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime		2020-05-25 10:09:05 -07:00
..
aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
asicworld
bram
errors
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana
liberty
lut
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories
opt	Merge pull request #1994 from YosysHQ/eddie/fix_bug1758	2020-05-14 11:56:22 -07:00
opt_share
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share
simple	Bugfix in partsel.v signed indices test cases	2020-05-02 11:21:01 +02:00
simple_abc9	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
smv
sva
svinterfaces
svtypes	support using previously declared types/localparams/params in package	2020-04-07 00:38:15 -04:00
techmap	tests: zinit for new types	2020-04-14 13:08:37 -07:00
tools
unit
various	xaiger: add testcase	2020-05-24 08:48:23 -07:00
verilog	Merge pull request #2057 from YosysHQ/eddie/fix_task_attr	2020-05-21 11:00:36 -07:00
vloghtb