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tests: tidy up testcase

This commit is contained in:
Eddie Hung 2020-06-03 08:41:55 -07:00
parent 00c5ceb1f2
commit 8a11019d38

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@ -7,9 +7,6 @@ always @*
assign q = ~l;
endmodule
EOT
proc
design -save gold
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9
select -assert-count 2 t:LUT4