clairexen 5428666151 Merge pull request #2186 from YosysHQ/mwk/dfflegalize ... Add dfflegalize pass.		2020-07-02 17:46:11 +02:00
..
aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	intel_alm: fix DFFE matching	2020-06-11 19:55:51 +02:00
asicworld
bram
errors
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana
liberty
lut
memfile
memories
opt	Add sub-assign and and-assign tests	2020-06-25 14:32:05 +02:00
opt_share	Support various binary operators in opt_share	2019-08-04 19:06:38 +02:00
proc
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share
simple	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
simple_abc9	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
smv
sva
svinterfaces
svtypes	static cast: add tests	2020-06-19 17:40:38 -07:00
techmap	dfflegalize: Add tests.	2020-07-01 01:57:15 +02:00
tools
unit
various	Merge pull request #2203 from antmicro/fix-grammar	2020-07-01 16:41:32 +02:00
verilog	Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings	2020-06-03 08:37:07 -07:00
vloghtb