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Merge pull request #2244 from antmicro/logic

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Add logic type support to parameters
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clairexen 2020-07-09 18:39:30 +02:00 • committed by GitHub
commit 802671b22e
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4 changed files with 31 additions and 7 deletions
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6
tests/various/integer_range_bad_syntax.ys Normal file
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logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT

6
tests/various/integer_real_bad_syntax.ys Normal file
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logger -expect error "syntax error, unexpected TOK_REAL" 1
read_verilog -sv <<EOT
module test_integer_real();
parameter integer real a = 0;
endmodule
EOT

9
tests/various/logic_param_simple.ys Normal file
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read_verilog -sv <<EOT
module test_logic_param();
parameter logic a = 0;
parameter logic [31:0] e = 0;
parameter logic signed b = 0;
parameter logic unsigned c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT