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Merge pull request #2203 from antmicro/fix-grammar

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Signed and macro grammar update
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clairexen 2020-07-01 16:41:32 +02:00 • committed by GitHub
commit 7450ee7f8a
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2 changed files with 38 additions and 4 deletions
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tests/various/signed.ys Normal file
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@ -0,0 +1,28 @@
# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT