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Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve

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abc9: -dff improvements
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Eddie Hung 2020-06-04 08:15:25 -07:00 • committed by GitHub
commit 69850204c4
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6 changed files with 143 additions and 55 deletions
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57
tests/arch/xilinx/abc9_dff.ys
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@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1
logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1
logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1
logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1
logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 8 t:FD*
@ -82,4 +82,53 @@ select -assert-count 1 t:FDPE
select -assert-count 2 t:INV
select -assert-count 0 t:FD* t:INV %% t:* %D
design -reset
read_verilog <<EOT
module top(input clk, input d, output q);
reg r;
always @(posedge clk) begin
r <= d;
end
assign q = ~r;
endmodule
EOT
proc
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDRE %co w:r %i
design -reset
read_verilog <<EOT
module top(input clk, input a, b, output reg q1, output q2);
reg r;
always @(posedge clk) begin
q1 <= a | b;
r <= ~(~a & ~b);
end
assign q2 = r;
endmodule
EOT
proc
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FDRE %co %a w:r %i
design -reset
read_verilog <<EOT
module top(input clk, input a, b, output o);
reg r1, r2;
always @(posedge clk) begin
r1 <= a | b;
r2 <= ~(~a & ~b);
end
assign o = r1 | r2;
endmodule
EOT
proc
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
logger -expect-no-warnings

3
tests/various/abc9.ys
View file

@ -97,4 +97,5 @@ select -assert-count 3 t:$_DFF_N_
select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
clean
select -assert-count 2 a:init
select -assert-none w:w w:z %% a:init %D
select -assert-count 1 w:w a:init %i
select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i