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Move combined assign tests to single file

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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-25 14:17:41 +02:00
parent 539087f417
commit 470df03f3d
4 changed files with 49 additions and 45 deletions
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49
tests/opt/opt_expr_combined_assign.ys Normal file
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@ -0,0 +1,49 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a |= i;
a |= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a += i;
a += j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a ^= i;
a ^= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i

15
tests/opt/opt_expr_or_assignment.ys
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@ -1,15 +0,0 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a |= i;
a |= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i

15
tests/opt/opt_expr_plus_assignment.ys
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@ -1,15 +0,0 @@
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a += i;
a += j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i

15
tests/opt/opt_expr_xor_assignment.ys
View file

@ -1,15 +0,0 @@
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a ^= i;
a ^= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i