Emil J. Tywoniak
36e91fc48f
tests: exclude signorm marker cells from two more cell-count assertions
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Same as eb32507cbhttps://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 16:52:45 +02:00
Emil J. Tywoniak
eb32507cb5
tests: exclude signorm marker cells from cell-count assertions
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$input_port, $output_port and $public are signorm bookkeeping rather than
mapped logic, so assertions counting "every cell" or "every $ cell" have
to subtract them -- as tests/opt/opt_expr_*.ys already do with
`t:$*_port %d t:$public %d`.
The memlib assertions are generated, so the fix goes in generate_mk.py
rather than the generated scripts.
These only differ once a design can still be in signorm mode when the
assertion runs; the subtraction is a no-op otherwise.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 14:05:18 +02:00
Emil J. Tywoniak
024a71626d
opt_expr: sub_not signorm compatibility
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Route the (2^k-1)-x -> ~x rewrite through OptExprPatcher like its
sibling transforms in this file, instead of raw module->Not +
module->connect + module->remove. Loosen the postopt assertion to
tolerate the $input_port shim cell bufnorm adds for the (still
signorm-active) input port, matching the t:$*_port %d idiom already
used by opt_expr_alu.ys and other sibling tests.
2026-07-20 16:40:46 +02:00
Emil J. Tywoniak
6b6847af51
tests/gatemate: update fsm LUT counts for new proc src mapping
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CC_LUT2 1 (was 2), CC_L2T4 max 15 (was 14) reflect the cell mapping
produced after the proc src-location changes.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
cf3867bb14
proc_mux: include switch expression location in $eq src
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(cherry picked from commit 383daa1eb3
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
c74bc43cfd
proc_mux, genrtlil: make use of case_src for better case condition vs block tracking
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(cherry picked from commit a24c260998
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
ea60c06c43
proc_dff: add wire src attributes to dff cells
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(cherry picked from commit 4072bcfd0b
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
707bac5208
proc_mux: add src test
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(cherry picked from commit a2e8e352b6
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
5cc17f5dd9
tests: undo skipping broken
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
f5b1bf0a9f
xprop test: use -readable dump
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
64337cf8a2
unit tests: twines
2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
92b16718c9
twine: fix replayability, reduce TwineSearch usage
2026-07-20 13:57:10 +02:00
Emil J. Tywoniak
fa55842c85
tests: skip broken
2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
77ad54139e
WIP
2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117
WIP
2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
f017bb8a93
twine
2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
8f207de2a7
WIP
2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
f7d40cf1a8
WIP
2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
fd67ce2b80
WIP
2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
0ff91a58d0
Revert "tests: use memory -bram-register in tests/bram"
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This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
e21e48397e
tests: use memory -bram-register in tests/bram
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
d19258cd51
fixup! tests: signorm fix
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
9eafc15df7
tests: signorm fix
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
eaa67e8d36
Revert "tests: use memory -bram-register in tests/bram"
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This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
1f745fb781
intel_alm: loosen tests
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
7cad14da7d
gowin: loosen tests
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
cc1bd1d4f1
ecp5: loosen tests
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
3de496e0c4
nexus: loosen tests
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
e313678594
xilinx_dsp: signorm compatibility
2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
71f01b23f8
tests: use memory -bram-register in tests/bram
2026-07-17 23:33:02 +02:00
Emil J. Tywoniak
e6dc9b4aba
tests: fix rtlil roundtrip test
2026-07-17 23:33:02 +02:00
Emil J. Tywoniak
2869f5bf9c
abstract: fix test signorm
2026-07-17 23:33:02 +02:00
Emil J. Tywoniak
04311dd529
tests: adjust to input_port and init behavior (sketchy)
2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
ae78170db8
tests: adjust to input_port and init behavior (sketchy)
2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
df0da642d2
tests: adjust to input_port and init behavior (sketchy)
2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
3031dd79d9
tests: adjust to input_port and init behavior (sketchy)
2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
328ffd79d0
bug2920: disable
2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
f50f03d972
tests: adjust to input_port and init behavior (sketchy)
2026-07-17 23:32:34 +02:00
nella
dddf137888
Merge pull request #6024 from YosysHQ/nella/scl-build-date
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Include build datetime in scl cache hash
2026-07-13 11:54:45 +00:00
nella
ede98b81ac
Merge pull request #6023 from b-michi/michaelbaier/sc-649/segmentation-fault-during-proc-init-with
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Michaelbaier/sc 649/segmentation fault during proc init with
2026-07-10 13:07:58 +00:00
nella
eb93f5a066
Add scl caching test.
2026-07-10 14:52:06 +02:00
Michael Baier
dca9234d86
Testcases for new truncation checks
2026-07-10 14:37:19 +02:00
Miodrag Milanovic
f2f3f31646
Add initial codecov support
2026-07-10 12:19:59 +02:00
Michael Baier
086c50763d
Tescases for Width Limit, Resize and Overflow
2026-07-09 14:34:56 +02:00
Michael Baier
3adb423e9e
Added Testcase for bug1206
2026-07-09 14:34:56 +02:00
Lofty
75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
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Move rename logic to abc_ops_reintegrate
2026-07-09 08:46:46 +00:00
nella
8dc32cbf4e
Merge pull request #6012 from YosysHQ/nella/fix-opt-reduce
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`opt_reduce`: restore pmux b-slice == a elim
2026-07-08 13:36:04 +00:00
nella
f6d810acf9
Restore pmux elim.
2026-07-08 11:58:30 +02:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
Miodrag Milanovic
8ad4ffcdd1
Cleanup
2026-07-08 08:34:01 +02:00
