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tests: exclude signorm marker cells from two more cell-count assertions

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Same as eb32507cb, for two `t:*` counts it missed. They only differ once
a design can still be in signorm mode when the assertion runs; the
subtraction is a no-op otherwise.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
This commit is contained in:
Emil J. Tywoniak 2026-07-21 16:52:45 +02:00
parent 3582b5df71
commit 36e91fc48f
2 changed files with 2 additions and 2 deletions
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2
tests/arch/ice40/ice40_opt.ys
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@ -24,7 +24,7 @@ EOT
read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:* t:$*_port %d t:$public %d
select -assert-count 1 t:$lut
# https://github.com/YosysHQ/yosys/issues/1543

2
tests/various/peepopt.ys
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@ -92,7 +92,7 @@ prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:*
select -assert-count 0 t:* t:$*_port %d t:$public %d
####################