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Emil J. Tywoniak 6b6847af51 tests/gatemate: update fsm LUT counts for new proc src mapping
CC_LUT2 1 (was 2), CC_L2T4 max 15 (was 14) reflect the cell mapping
produced after the proc src-location changes.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 15:01:30 +02:00
..
aiger
alumacc
arch tests/gatemate: update fsm LUT counts for new proc src mapping 2026-07-20 15:01:30 +02:00
arith_tree
asicworld
bind
blif
bram Revert "tests: use memory -bram-register in tests/bram" 2026-07-17 23:38:01 +02:00
bugpoint
check_mem
cxxrtl
errors
fmt
fsm
functional
hana
liberty Add scl caching test. 2026-07-10 14:52:06 +02:00
lut
memfile
memlib
memories twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
opt WIP 2026-07-17 23:48:54 +02:00
opt_share
peepopt
proc proc_mux: include switch expression location in $eq src 2026-07-20 15:01:30 +02:00
pyosys
realmath
rpc
rtlil twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
sat
sdc
select
share
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap WIP 2026-07-17 23:48:54 +02:00
tools
unit unit tests: twines 2026-07-20 15:01:30 +02:00
various twine 2026-07-20 12:26:39 +02:00
verific
verilog Rm. 2026-07-07 04:03:17 +02:00
vloghtb
write_verilog
xprop xprop test: use -readable dump 2026-07-20 15:01:30 +02:00
.gitignore
common.mk
gen_tests_makefile.py tests: undo skipping broken 2026-07-20 15:01:30 +02:00
Makefile Add initial codecov support 2026-07-10 12:19:59 +02:00
pass-fuzzing.md