3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-10 08:01:14 +00:00
yosys/tests
2026-07-17 23:32:34 +02:00
..
aiger
alumacc
arch Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 2026-07-09 08:46:46 +00:00
arith_tree
asicworld
bind
blif
bram Add initial codecov support 2026-07-10 12:19:59 +02:00
bugpoint
check_mem
cxxrtl
errors
fmt
fsm
functional
hana
liberty Add scl caching test. 2026-07-10 14:52:06 +02:00
lut
memfile
memlib
memories
opt tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
opt_share
peepopt
proc
pyosys
realmath
rpc
rtlil Testcases for new truncation checks 2026-07-10 14:37:19 +02:00
sat
sdc
select
share
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap
tools
unit Tescases for Width Limit, Resize and Overflow 2026-07-09 14:34:56 +02:00
various Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 2026-07-09 08:46:46 +00:00
verific
verilog
vloghtb
write_verilog
xprop
.gitignore
common.mk
gen_tests_makefile.py
Makefile Add initial codecov support 2026-07-10 12:19:59 +02:00
pass-fuzzing.md