1551 commits

Author	SHA1	Message	Date
David Shah	13424352cc	Merge pull request #1332 from YosysHQ/dave/ecp5gsr ... ecp5: Add GSR and SGSR support	2019-08-28 12:44:02 +01:00
Marcin Kościelnicki	d361f5ab79	xilinx: Add SRLC16E primitive. ... Fixes #1331.	2019-08-27 20:27:12 +02:00
David Shah	fc001b4731	ecp5: Add GSR support ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-27 13:07:06 +01:00
Eddie Hung	1ba09c4ab7	Merge branch 'master' into eddie/xilinx_srl	2019-08-26 13:56:31 -07:00
Eddie Hung	a098205479	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-26 13:25:17 -07:00
Eddie Hung	d7051b90de	Add undocumented feature	2019-08-23 16:41:32 -07:00
Eddie Hung	455da57272	Fix spacing	2019-08-23 13:21:21 -07:00
Eddie Hung	85d39653ac	Remove unused model	2019-08-23 13:20:29 -07:00
Eddie Hung	08139aa53a	xilinx_srl now copes with word-level flops $dff{,e}	2019-08-23 12:22:46 -07:00
Eddie Hung	78b7d8f531	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-23 11:32:44 -07:00
Eddie Hung	e658d472c8	Put attributes above port	2019-08-23 11:31:20 -07:00
Eddie Hung	d672b1ddec	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-23 11:26:55 -07:00
Eddie Hung	20f4d191b5	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-23 11:24:19 -07:00
Eddie Hung	509c353fe9	Forgot one	2019-08-23 11:23:50 -07:00
Eddie Hung	0d0ad15898	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-23 11:23:31 -07:00
Eddie Hung	a270af00cc	Put abc_* attributes above port	2019-08-23 11:21:44 -07:00
Eddie Hung	6872805a3e	Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap	2019-08-23 10:00:50 -07:00
Eddie Hung	7188972645	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:54 -07:00
Clifford Wolf	151db528e4	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:09:37 +02:00
Clifford Wolf	2c8c8b3c74	Merge pull request #1289 from mmicko/anlogic_fixes ... Anlogic fixes and optimization	2019-08-22 18:09:10 +02:00
Clifford Wolf	4c449caf9b	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:06:36 +02:00
Clifford Wolf	4d37710e82	Merge pull request #1281 from mmicko/efinix ... Initial support for Efinix Trion series FPGAs	2019-08-22 18:06:02 +02:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	edec73fec1	abc9 to perform new 'map_ffs' before 'map_luts'	2019-08-21 15:37:55 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00
Eddie Hung	c7af71ecde	Use semicolon	2019-08-21 11:47:17 -07:00
Eddie Hung	5d0f6cbd54	techmap before read	2019-08-21 11:47:06 -07:00
Eddie Hung	8f69be9cc7	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-21 11:39:14 -07:00
Eddie Hung	584c680691	Add abc_arrival to SRL*	2019-08-21 11:27:42 -07:00
Eddie Hung	076af2e617	Missing newline	2019-08-20 20:37:52 -07:00
Eddie Hung	b7a48e3e0f	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-20 20:18:17 -07:00
Eddie Hung	64d62710de	Oops	2019-08-20 20:07:38 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
Eddie Hung	6b1b03d9f7	ecp5: remove DPR16X4 from abc_unmap.v	2019-08-20 19:20:17 -07:00
Eddie Hung	d46dc9c5b4	ecp5 to use -max_iter 1	2019-08-20 19:18:36 -07:00
Eddie Hung	55acf3120f	ecp5 to use abc_map.v and _unmap.v	2019-08-20 18:59:03 -07:00
Eddie Hung	343039496b	Add reference to FD* timing	2019-08-20 18:22:58 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	bbab608691	Remove SRL* delays from cells_sim.v	2019-08-20 18:14:40 -07:00
Eddie Hung	aa2d3af631	LUTMUX -> LUTMUX6	2019-08-20 18:08:07 -07:00
Eddie Hung	30a379b5b6	Cleanup techmap in map_luts	2019-08-20 17:59:31 -07:00
Eddie Hung	3b52d6e29c	Move techmap abc_map.v into map_luts	2019-08-20 17:55:12 -07:00
Eddie Hung	54284aaa98	Remove delays from abc_map.v	2019-08-20 17:52:27 -07:00
Eddie Hung	96f00e9147	Typo	2019-08-20 17:51:50 -07:00
Eddie Hung	8f666ebac1	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 17:36:14 -07:00
Eddie Hung	e273ed5275	Wrap SRL{16,32} too	2019-08-20 15:09:38 -07:00
Eddie Hung	808f07630f	Wrap LUTRAMs in order to capture comb/seq behaviour	2019-08-20 14:49:11 -07:00
Eddie Hung	0079e9b4a6	Add LUTRAM delays	2019-08-20 13:53:38 -07:00
Eddie Hung	8d0cffaf20	Remove mapping rules	2019-08-20 13:11:39 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00