3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-08 10:25:19 +00:00

Fix spacing

This commit is contained in:
Eddie Hung 2019-08-23 13:21:21 -07:00
parent 85d39653ac
commit 455da57272

View file

@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
input WCK,
input [3:0] RAD,
/* (* abc_arrival=<TODO> *) */
output [3:0] DO
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";