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Code Activity
yosys/techlibs
History
Eddie Hung 8f69be9cc7 Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-21 11:39:14 -07:00
..
achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
common Missing newline 2019-08-20 20:37:52 -07:00
coolrunner2 Fix spacing 2019-08-06 16:47:55 -07:00
easic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ecp5 ecp5: remove DPR16X4 from abc_unmap.v 2019-08-20 19:20:17 -07:00
gowin Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
greenpak4 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ice40 Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 2019-08-20 11:59:31 -07:00
intel techlibs/intel: Clean up Makefile 2019-08-05 11:22:11 -07:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx Add abc_arrival to SRL* 2019-08-21 11:27:42 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00