5007 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	ea41e61a36	utils: add BitGrouper for shared bit-partition logic	2026-06-10 14:53:13 +02:00
Emil J. Tywoniak	d952b04e54	opt_expr: convert remaining rewrites to patcher	2026-06-10 14:53:05 +02:00
Emil J. Tywoniak	e2a77db87a	opt_expr: evener morer patcherer	2026-06-10 14:53:03 +02:00
Emil J. Tywoniak	edeb649154	opt_expr: even more patcher	2026-06-10 14:53:02 +02:00
Emil J. Tywoniak	fb021b1a6b	opt_expr: more patcher again	2026-06-10 14:53:00 +02:00
Emil J. Tywoniak	c3457e2e5c	WIP	2026-06-10 14:52:50 +02:00
Emil J. Tywoniak	dab9a386cc	opt_expr: WIP use patcher more	2026-05-28 22:51:30 +02:00
Emil J. Tywoniak	b594196a48	opt_expr: cleanup	2026-05-28 14:56:27 +02:00
Emil J. Tywoniak	5cdb189ea0	opt_expr: cleanup	2026-05-28 14:53:21 +02:00
Emil J. Tywoniak	cef8186c4a	patch: infer leaves for gc	2026-05-28 12:56:13 +02:00
Emil J. Tywoniak	1cd0d37511	patch: instead of cell->cell, use port->sig rewrites	2026-05-27 18:07:01 +02:00
Emil J. Tywoniak	b3a33aeeba	opt_expr: use patcher for xor constant folding	2026-05-27 18:06:55 +02:00
Emil J. Tywoniak	9f22b9d2a0	patch: source transfer	2026-05-23 00:10:02 +02:00
Emil J. Tywoniak	db1c1d4359	patch: working multi-cell signorm invariant	2026-05-23 00:10:00 +02:00
Emil J. Tywoniak	8c26ecd2a6	patch: WIP multicell patch test	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	d2ae9b48e4	patch: signorm, move	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	b7ea32dbee	patch: unique heap	2026-05-23 00:09:17 +02:00
Emil J. Tywoniak	89e5c4ccca	test_patch total basics	2026-05-23 00:07:39 +02:00
Emil J. Tywoniak	dcc68e49fb	check: check bufnorm too	2026-05-22 18:41:50 +02:00
Emil J. Tywoniak	4bff2e6340	check: check signorm indices and wires	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	8f62d5c657	opt_merge: newcelltypes	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	7d335ed0d9	opt_merge: factor out hashing code across incremental and parallel	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	9abee44602	opt_expr: replace invert_map with signorm traversal	2026-05-22 18:41:49 +02:00
Emil J. Tywoniak	350385f5a2	check: fix memory bug in $connect	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	1dc7a69d7f	memory_bram: create blackboxes	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	8c4ab49955	Revert "memory: add -bram-register" ... This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	c64be26334	Revert "memory_bram: add -register" ... This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	09f55abf1a	flatten: disable signorm	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	6fd7f5c02d	pmgen: hold sigmap pointer instead of owning it	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	394be03d57	equiv_miter: don't copy $input_port	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	451e01d0a4	design: properly switch signorm mode when restoring saved designs	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	38fab51fc1	equiv_make: don't copy $input_port	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	a93faf811a	Revert "techmap: call hierarchy on map files to determine port directions" ... This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	81b99d83f5	hierarchy: tolerance for apparent recursive instances in techmap files	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	0eb215dd97	techmap: call hierarchy on map files to determine port directions	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	67de0c8c9e	memory: add -bram-register	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	88aa5f190b	memory_bram: add -register	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	5bfb631085	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	bd8738de15	connect: remove input ports on conflict	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	aecc173f83	opt_dff: sigma harder, FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	be7beaf91a	opt_dff: temporarily disable signorm due to muxtree traversal	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	21bed1a411	design: fix signorm commit connectivity to design	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	faa1a1065c	flatten: redo signormalization to work around fanout issue	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4f665d6efc	signorm: disable passes that use rewrite_sigspecs	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	8267dee75a	check: stitch info about $connect ports together for driver analysis	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	5c5df513d1	abstract: skip $input_port cells	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	dad6277a25	flatten: skip $input_port cells in template module	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	68bb5c6b94	signorm: disable in passes that use swap_names	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4d2a6f2b7a	opt_expr: fix invert_map	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	b859080ef2	techmap: disable signorm more	2026-05-22 18:37:58 +02:00