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patch: working multi-cell signorm invariant

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This commit is contained in:
Emil J. Tywoniak 2026-05-19 18:48:43 +02:00
parent e78e19acfe
commit db1c1d4359
3 changed files with 35 additions and 52 deletions
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15
passes/cmds/test_patch.cc
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@ -20,19 +20,16 @@ struct TestPatchPass : public Pass {
Cell* add = cell;
log_assert(add->getPort(ID::B).is_wire());
log_assert(add->getPort(ID::B).known_driver());
auto neg = add->getPort(ID::B).as_wire()->driverCell();
auto neg = add->getPort(ID::B)[0].wire->driverCell();
log_assert(neg->type == ID($not));
RTLIL::Patch patcher;
patcher.mod = module;
patcher.map = SigMap(module);
auto new_cell = patcher.addNeg(NEW_ID, patcher.Sub(NEW_ID, neg->getPort(ID::A), cell->getPort(ID::A)), SigSpec());
// // sub->connections_ = cell->connections();
// sub->parameters = add->parameters;
// sub->connections_[ID::A] = add->getPort(ID::A);
// sub->connections_[ID::B] = add->getPort(ID::B);
// sub->connections_[ID::Y] = add->getPort(ID::Y);
auto sub = patcher.addSub(NEW_ID,
neg->getPort(ID::A),
cell->getPort(ID::A),
patcher.addWire(NEW_ID, cell->getPort(ID::A).size()));
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), SigSpec());
log_cell(new_cell);
patcher.patch(add, new_cell);
}