mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 19:36:21 +00:00
Code Activity

abstract: skip $input_port cells

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-03-17 16:34:41 +01:00
parent dad6277a25
commit 5c5df513d1
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/abstract.cc
View file

@ -265,6 +265,8 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
unsigned int changed = 0;
std::vector<Cell*> cells_snapshot = mod->cells();
for (auto cell : cells_snapshot) {
if (cell->type == ID($input_port))
continue;
for (auto conn : cell->connections())
if (cell->output(conn.first)) {
std::set<int> offsets_to_abstract;