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pmgen: hold sigmap pointer instead of owning it

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This commit is contained in:
Emil J. Tywoniak 2026-04-14 18:05:33 +02:00
parent 394be03d57
commit 6fd7f5c02d
10 changed files with 58 additions and 40 deletions
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3
passes/opt/peepopt.cc
View file

@ -101,11 +101,12 @@ struct PeepoptPass : public Pass {
{
did_something = true;
SigMap sigmap(module);
while (did_something)
{
did_something = false;
peepopt_pm pm(module);
peepopt_pm pm(module, &sigmap);
pm.setup(module->selected_cells());

3
passes/pmgen/generate.h
View file

@ -85,7 +85,8 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
if (timeout++ > 10000)
log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n");
pm matcher(mod, mod->cells());
SigMap sigmap(mod);
pm matcher(mod, &sigmap, mod->cells());
matcher.rng(1);
matcher.rngseed += modcnt;

18
passes/pmgen/pmgen.py
View file

@ -361,7 +361,7 @@ with open(outfile, "w") as f:
print("struct {}_pm {{".format(prefix), file=f)
print(" Module *module;", file=f)
print(" SigMap sigmap;", file=f)
print(" SigMap *sigmap;", file=f)
print(" std::function<void()> on_accept;", file=f)
print(" bool setup_done;", file=f)
print(" bool generate_mode;", file=f)
@ -423,7 +423,7 @@ with open(outfile, "w") as f:
print("", file=f)
print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
print(" for (auto bit : sigmap(sig)) {", file=f)
print(" for (auto bit : (*sigmap)(sig)) {", file=f)
print(" if (bit.wire == nullptr) continue;", file=f)
print(" sigusers[bit].insert(cell);", file=f)
print(" }", file=f)
@ -453,12 +453,12 @@ with open(outfile, "w") as f:
print(" SigSpec port(Cell *cell, IdString portname) {", file=f)
print(" try {", file=f)
print(" return sigmap(cell->getPort(portname));", file=f)
print(" return (*sigmap)(cell->getPort(portname));", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f)
print(" return sigmap(cell->connections_.at(portname, defval));", file=f)
print(" return (*sigmap)(cell->connections_.at(portname, defval));", file=f)
print(" }", file=f)
print("", file=f)
@ -475,21 +475,21 @@ with open(outfile, "w") as f:
print(" int nusers(const SigSpec &sig) {", file=f)
print(" pool<Cell*> users;", file=f)
print(" for (auto bit : sigmap(sig))", file=f)
print(" for (auto bit : (*sigmap)(sig))", file=f)
print(" for (auto user : sigusers[bit])", file=f)
print(" users.insert(user);", file=f)
print(" return GetSize(users);", file=f)
print(" }", file=f)
print("", file=f)
print(" {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f)
print(" {}_pm(Module *module, SigMap *map, const vector<Cell*> &cells) :".format(prefix), file=f)
print(" module(module), sigmap(map), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f)
print(" setup(cells);", file=f)
print(" }", file=f)
print("", file=f)
print(" {}_pm(Module *module) :".format(prefix), file=f)
print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f)
print(" {}_pm(Module *module, SigMap *map) :".format(prefix), file=f)
print(" module(module), sigmap(map), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f)
print(" }", file=f)
print("", file=f)

18
passes/pmgen/test_pmgen.cc
View file

@ -163,8 +163,10 @@ struct TestPmgenPass : public Pass {
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
while (test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_chain)) {}
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
while (test_pmgen_pm(module, &sigmap, module->selected_cells()).run_reduce(reduce_chain)) {}
}
}
void execute_reduce_tree(std::vector<std::string> args, RTLIL::Design *design)
@ -182,8 +184,10 @@ struct TestPmgenPass : public Pass {
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
test_pmgen_pm(module, &sigmap, module->selected_cells()).run_reduce(reduce_tree);
}
}
void execute_eqpmux(std::vector<std::string> args, RTLIL::Design *design)
@ -201,8 +205,10 @@ struct TestPmgenPass : public Pass {
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
test_pmgen_pm(module, module->selected_cells()).run_eqpmux(opt_eqpmux);
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
test_pmgen_pm(module, &sigmap, module->selected_cells()).run_eqpmux(opt_eqpmux);
}
}
void execute_generate(std::vector<std::string> args, RTLIL::Design *design)