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opt_expr: use patcher for xor constant folding
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1 changed files with 15 additions and 8 deletions
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@ -23,6 +23,7 @@
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#include "kernel/newcelltypes.h"
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#include "kernel/utils.h"
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#include "kernel/log.h"
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#include "kernel/unstable/patch.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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@ -617,17 +618,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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log_abort();
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}
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if (!sig_a.wire)
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auto port_a = ID::A;
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if (!sig_a.wire) {
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std::swap(sig_a, sig_b);
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port_a = ID::B;
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}
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if (sig_b == State::S0 || sig_b == State::S1) {
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if (cell->type.in(ID($xor), ID($_XOR_))) {
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SigSpec sig_y;
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if (cell->type == ID($xor))
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sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
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else if (cell->type == ID($_XOR_))
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sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
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else log_abort();
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
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if (sig_b == State::S0) {
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_a);
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} else {
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RTLIL::Patch patcher;
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patcher.mod = module;
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Wire* y = patcher.addWire(NEW_ID, cell->type == ID($xor) ? cell->getParam(ID::Y_WIDTH).as_int() : 1);
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Cell* new_cell = cell->type == ID($xor) ? patcher.addNot(NEW_ID, sig_a, y) : patcher.addNotGate(NEW_ID, sig_a, y);
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patcher.leaves = {cell->getPort(port_a).as_wire()};
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patcher.patch(cell, new_cell);
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}
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goto next_cell;
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}
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if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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