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https://github.com/YosysHQ/yosys
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memory_bram: create blackboxes
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1 changed files with 63 additions and 0 deletions
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@ -125,6 +125,55 @@ struct rules_t
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variant_params[stringf("\\CFG_CLKPOL_%c", 'A' + i)] = clkpol[i];
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}
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}
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void load_blackbox(Design* design) const
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{
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auto portinfos = make_portinfos();
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int clocks_max = 0;
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for (auto &pi : portinfos)
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clocks_max = max(clocks_max, pi.clocks);
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pool<std::pair<IdString, int>> inputs;
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pool<std::pair<IdString, int>> outputs;
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for (auto &pi : portinfos)
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{
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string prefix = stringf("%c%d", pi.group + 'A', pi.index + 1);
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const char *pf = prefix.c_str();
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if (pi.clocks) {
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std::string name = stringf("\\CLK%d", (pi.clocks-1) % clocks_max + 1);
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inputs.insert(std::make_pair(name, 1));
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}
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inputs.insert(std::make_pair(stringf("\\%sADDR", pf), abits));
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std::string dname = stringf("\\%sDATA", pf);
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if (pi.wrmode) {
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inputs.insert(std::make_pair(dname, dbits));
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} else {
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outputs.insert(std::make_pair(dname, dbits));
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}
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if (pi.enable) {
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std::string name = stringf("\\%sEN", pf);
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inputs.insert(std::make_pair(name, 1));
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}
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}
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log_debug("setting up %s\n", name);
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Module* mod = design->addModule(name);
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mod->set_bool_attribute(ID::blackbox);
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for (auto [name, width] : inputs)
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{
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log_debug("input %s width %d\n", name, width);
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mod->addWire(name, width)->port_input = true;
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}
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for (auto [name, width] : outputs)
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{
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log_debug("output %s width %d\n", name, width);
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mod->addWire(name, width)->port_output = true;
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}
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mod->fixup_ports();
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}
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};
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struct match_t {
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@ -160,6 +209,19 @@ struct rules_t
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vector<string> labels;
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int linecount;
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void load_blackboxes(Design* design) const
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{
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for (auto& [_, variants] : brams)
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{
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for (const bram_t& bram : variants)
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{
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if (design->module(bram.name))
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continue;
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bram.load_blackbox(design);
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}
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}
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}
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void syntax_error()
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{
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if (tokens.empty())
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@ -1314,6 +1376,7 @@ struct MemoryBramPass : public Pass {
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-rules" && argidx+1 < args.size()) {
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rules.parse(args[++argidx]);
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rules.load_blackboxes(design);
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continue;
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}
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break;
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