mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 03:16:22 +00:00
Code Activity

equiv_make: don't copy $input_port

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-04-08 11:40:19 +02:00
parent 7905df89f3
commit 38fab51fc1
1 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/equiv/equiv_make.cc
View file

@ -115,6 +115,8 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, it->name.str() + "_gold");
if (it->type == ID($input_port))
gold_clone->remove(it);
}
for (auto it : gate_clone->wires().to_vector()) {
@ -127,6 +129,8 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, it->name.str() + "_gate");
if (it->type == ID($input_port))
gate_clone->remove(it);
}
gold_clone->cloneInto(equiv_mod);
@ -514,6 +518,7 @@ struct EquivMakePass : public Pass {
worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
worker.run();
Pass::call(design, "dump");
}
} EquivMakePass;