mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 07:32:32 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/abstract.cc
View file

@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
unsigned int changed = 0;
std::vector<Cell*> cells_snapshot = mod->cells();
for (auto cell : cells_snapshot) {
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto conn : cell->connections())
if (cell->output(conn.first)) {

2
passes/cmds/check.cc
View file

@ -358,7 +358,7 @@ struct CheckPass : public Pass {
pool<Cell *> coarsened_cells;
for (auto cell : module->cells())
{
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {

2
passes/cmds/portarcs.cc
View file

@ -125,7 +125,7 @@ struct PortarcsPass : Pass {
for (auto cell : m->cells())
// Ignore all bufnorm helper cells
if (!cell->type.in(ID($buf), ID($input_port), ID($connect), ID($tribuf))) {
if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) {
auto tdata = tinfo.find(cell->type);
if (tdata == tinfo.end())
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());

4
passes/equiv/equiv_make.cc
View file

@ -115,7 +115,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, it->name.str() + "_gold");
if (it->type == ID($input_port))
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
gold_clone->remove(it);
}
@ -129,7 +129,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, it->name.str() + "_gate");
if (it->type == ID($input_port))
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
gate_clone->remove(it);
}

2
passes/equiv/equiv_miter.cc
View file

@ -143,7 +143,7 @@ struct EquivMiterWorker
for (auto w : miter_wires)
miter_module->addWire(w->name, w->width);
for (auto c : miter_cells) {
if (c->type == ID($input_port))
if (c->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
auto mc = miter_module->addCell(c->name, c);
for (auto &conn : mc->connections())

2
passes/fsm/fsm_detect.cc
View file

@ -99,6 +99,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
continue;
if (cellport.second != ID::A && cellport.second != ID::B)

2
passes/hierarchy/flatten.cc
View file

@ -178,7 +178,7 @@ struct FlattenWorker
}
for (auto tpl_cell : tpl->cells()) {
if (tpl_cell->type == ID($input_port))
if (tpl_cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell);
map_attributes(cell, new_cell, tpl_cell->name);

14
passes/opt/opt_clean/cells_temp.cc
View file

@ -50,9 +50,9 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections,
}
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
// Removing $connect and $input_port doesn't count as "doing something"
// since they get rebuilt in signorm
// and don't enable further opt
// Removing $connect, $input_port, $output_port and $public doesn't count
// as "doing something" since they get rebuilt in signorm and don't enable
// further opt
bool did_something = false;
for (RTLIL::Cell *cell : cells) {
if (verbose) {
@ -62,6 +62,12 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
@ -93,7 +99,7 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
std::swap(a, b);
new_connections.insert(ctx, {a, b});
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) {
delcells.insert(ctx, cell);
}
}

2
passes/opt/opt_merge_inc.cc
View file

@ -52,6 +52,8 @@ static constexpr MergeableTypes build_mergeable_types(bool nomux) {
c.set_id(ID($allconst), false);
c.set_id(ID($connect), false);
c.set_id(ID($input_port), false);
c.set_id(ID($output_port), false);
c.set_id(ID($public), false);
if (nomux) {
c.set_id(ID($mux), false);
c.set_id(ID($pmux), false);

5
passes/opt/opt_share.cc
View file

@ -363,10 +363,13 @@ struct OptSharePass : public Pass {
dict<RTLIL::SigBit, int> bit_users;
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto conn : cell->connections())
for (auto bit : conn.second)
bit_users[sigmap(bit)]++;
}
for (auto wire : module->wires())
if (wire->port_id != 0)

3
passes/sat/sim.cc
View file

@ -602,6 +602,9 @@ struct SimInstance
if (cell->type == ID($print))
return;
if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect)))
return;
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
}

5
passes/techmap/arith_tree.cc
View file

@ -29,11 +29,14 @@ struct Traversal {
dict<SigBit, int> fanout;
Traversal(Module *module) : sigmap(module)
{
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto &conn : cell->connections())
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
bit_consumers[bit].insert(cell);
}
for (auto &pair : bit_consumers)
fanout[pair.first] = pair.second.size();