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patch: source transfer

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This commit is contained in:
Emil J. Tywoniak 2026-05-19 19:31:16 +02:00
parent db1c1d4359
commit 9f22b9d2a0
5 changed files with 68 additions and 6 deletions
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9
kernel/rtlil.cc
View file

@ -952,7 +952,7 @@ string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
return value;
}
void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
std::string RTLIL::AttrObject::strpool_attribute_to_str(const pool<string> &data)
{
string attrval;
for (const auto &s : data) {
@ -960,7 +960,12 @@ void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<str
attrval += "|";
attrval += s;
}
set_string_attribute(id, attrval);
return attrval;
}
void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
{
set_string_attribute(id, strpool_attribute_to_str(data));
}
void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)

1
kernel/rtlil.h
View file

@ -1279,6 +1279,7 @@ struct RTLIL::AttrObject
void set_string_attribute(RTLIL::IdString id, string value);
string get_string_attribute(RTLIL::IdString id) const;
static std::string strpool_attribute_to_str(const pool<string> &data);
void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
pool<string> get_strpool_attribute(RTLIL::IdString id) const;

49
kernel/unstable/patch.cc
View file

@ -54,7 +54,54 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
return wire;
}
void Patch::collect_src(Cell* old_cell) {
src.insert(old_cell->get_src_attribute());
log("collect %s\n", old_cell->name);
std::vector<Cell*> inputs = {};
for (auto [port_name, sig] : old_cell->connections()) {
auto dir = old_cell->port_dir(port_name);
log_assert(dir != PD_UNKNOWN);
log_assert(!sig.size() || sig.is_wire());
if (dir == PD_INPUT || dir == PD_INOUT) {
Wire* in_wire = sig.as_wire();
if (!leaves.count(in_wire))
inputs.push_back(in_wire->driverCell());
}
}
for (auto input : inputs)
collect_src(input);
}
void Patch::gc(Cell* old_cell) {
log("gc %s\n", old_cell->name);
std::vector<Cell*> inputs = {};
for (auto [port_name, sig] : old_cell->connections()) {
auto dir = old_cell->port_dir(port_name);
log_assert(dir != PD_UNKNOWN);
log_assert(!sig.size() || sig.is_wire());
if (dir == PD_OUTPUT || dir == PD_INOUT) {
if (sig.size()) {
for (auto bit : sig) {
// Reject GC if used
if (!mod->fanout(bit).empty())
return;
}
}
}
if (dir == PD_INPUT || dir == PD_INOUT) {
Wire* in_wire = sig.as_wire();
if (!leaves.count(in_wire))
inputs.push_back(in_wire->driverCell());
}
}
for (auto input : inputs)
gc(input);
}
void Patch::patch(Cell* old_cell, Cell* new_cell) {
log_assert(!leaves.empty());
collect_src(old_cell);
std::string src_str = AttrObject::strpool_attribute_to_str(src);
for (auto& wire: wires_) {
wire->module = mod;
Wire* raw = wire.release();
@ -64,6 +111,7 @@ void Patch::patch(Cell* old_cell, Cell* new_cell) {
log_cell(old_cell);
for (auto& cell: cells_) {
log_cell(cell.get());
cell->set_src_attribute(src_str);
Cell* raw = cell.release();
mod->cells_[raw->name] = raw;
for (auto [port_name, sig] : raw->connections()) {
@ -91,6 +139,7 @@ void Patch::patch(Cell* old_cell, Cell* new_cell) {
raw->fixup_parameters();
}
log_module(mod, "");
gc(old_cell);
}

10
kernel/unstable/patch.h
View file

@ -11,6 +11,10 @@ struct RTLIL::Patch final : public CellAdderMixin<RTLIL::Patch>
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
private:
void collect_src(Cell* old_cell);
void gc(Cell* old_cell);
protected:
void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell);
@ -18,12 +22,14 @@ protected:
public:
Module *mod;
SigMap map;
// SigMap map;
vector<std::unique_ptr<Wire>> wires_;
vector<std::unique_ptr<Cell>> cells_;
Cell* root;
pool<Wire*> leaves;
vector<RTLIL::SigSig> connections_;
// vector<RTLIL::SigSig> connections_;
pool<string> src;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);

5
passes/cmds/test_patch.cc
View file

@ -24,13 +24,14 @@ struct TestPatchPass : public Pass {
log_assert(neg->type == ID($not));
RTLIL::Patch patcher;
patcher.mod = module;
patcher.map = SigMap(module);
auto sub = patcher.addSub(NEW_ID,
neg->getPort(ID::A),
cell->getPort(ID::A),
add->getPort(ID::A),
patcher.addWire(NEW_ID, cell->getPort(ID::A).size()));
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), SigSpec());
log_cell(new_cell);
patcher.leaves.insert(neg->getPort(ID::A).as_wire());
patcher.leaves.insert(add->getPort(ID::A).as_wire());
patcher.patch(add, new_cell);
}
}