Emil J. Tywoniak
b08441d95c
clockgate: shuffle test liberty to exercise comparison better
2024-11-18 12:48:50 +01:00
Emil J. Tywoniak
1e3f8cc630
clockgate: add test liberty file
2024-11-18 12:45:27 +01:00
Emil J. Tywoniak
c921d85a85
clockgate: fix test comments
2024-11-18 12:33:09 +01:00
Martin Povišer
0d5c412807
read_liberty: s/busses/buses/
2024-11-12 13:33:41 +01:00
Martin Povišer
56a9202a97
Add read_liberty tests of new options
2024-11-12 13:29:16 +01:00
Martin Povišer
5a0cb5d453
Check in filtered samples of IHP's Liberty data for tests
2024-11-12 13:28:15 +01:00
Martin Povišer
1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
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peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
mszelwiga
8e508f2a2a
Fix setting bits of parameters in setundef pass
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This commit also adds test that verifies correctness of this change.
2024-11-08 17:03:08 +01:00
Martin Povišer
e82e5f8b13
rtlil: Adjust internal check for $mem_v2 cells
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There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.
The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.
Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.
This breaks RTLIL compatibility but for an obscure edge case.
2024-11-08 15:18:43 +01:00
Miodrag Milanovic
df391f5816
verific: fix blackbox regression and add test case
2024-11-08 14:57:04 +01:00
KrystalDelusion
4343c791cb
Merge pull request #4704 from YosysHQ/krys/drop_ilang
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Remove references to ilang
2024-11-08 11:28:06 +13:00
George Rennie
a31c968340
tests/bufnorm: add test for bufnorm of constant
2024-11-07 12:55:50 +01:00
George Rennie
c23e64a236
tests/proc: add proc_dff bug 4712 as testcase
2024-11-07 00:10:17 +01:00
N. Engelhardt
2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing
2024-11-06 16:29:07 +01:00
N. Engelhardt
9068ec5566
Merge pull request #4627 from RCoeurjoly/roland/assume_x
2024-11-06 16:27:30 +01:00
Martin Povišer
69a36aec3b
Add keep_hierarchy test
2024-11-05 09:28:45 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
Lofty
3250f2b82b
Merge pull request #4700 from povik/select-list-mod
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Add `select -list-mod`
2024-11-04 15:38:42 +00:00
Martin Povišer
d752ca4847
Fix test after option change
2024-11-04 16:26:46 +01:00
Martin Povišer
f7400a06cd
Fix test
2024-11-04 16:19:59 +01:00
Martin Povišer
23922faecc
Test new Tcl methods
2024-11-04 16:18:50 +01:00
Martin Povišer
c9ed6d8dcf
cellmatch: Rename -lut_attrs to -derive_luts; document option
2024-11-04 14:28:40 +01:00
Martin Povišer
7aa3fdab80
select: Add -list-mod option
2024-11-04 13:16:13 +01:00
Martin Povišer
9432e972f7
Merge pull request #4626 from povik/select-t-at
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select: Add new `t:@<name>` syntax
2024-10-16 10:18:05 +02:00
Emil J. Tywoniak
f9f509bc25
select: add t:@<name> test
2024-10-15 21:06:06 +02:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Miodrag Milanović
ecec156965
Merge pull request #4643 from donn/fix_wheels
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wheels: fix missing yosys-abc/share directory
2024-10-09 18:05:58 +02:00
Emil J
038e262332
Merge pull request #4624 from YosysHQ/emil/cxxrtl-smoke-test
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cxxrtl: test stream operator
2024-10-09 05:57:13 -07:00
Mohamed Gaber
3d6b8b8e1a
wheels: fix missing yosys-abc/share directory
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* `misc/__init__.py`:
* checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc`
* checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname`
* `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled
* `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled
* `Makefile`: add new target, `share`, to only create the extra targets
* `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build
* `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI
2024-10-09 13:09:14 +03:00
Martin Povišer
e46cc57cc4
Merge pull request #4613 from povik/err-never-silence
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log: Never silence `log_cmd_error`
2024-10-07 16:12:31 +02:00
Martin Povišer
0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay
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read_liberty: Optionally import unit delay arcs
2024-10-07 16:11:51 +02:00
Martin Povišer
74e92d10e8
Merge pull request #4593 from povik/aiger2
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New aiger backend
2024-10-07 16:11:25 +02:00
Martin Povišer
6c1450fdaf
Merge pull request #4607 from povik/ql-nodiv
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quicklogic: Avoid carry chains in division mapping
2024-10-07 16:11:11 +02:00
Martin Povišer
ca5c2fdff1
quicklogic: Relax the LUT number test
2024-10-07 15:27:03 +02:00
Martin Povišer
b01b17689e
Add test of error not getting silenced
2024-10-07 14:49:17 +02:00
Martin Povišer
d0a11e26f3
aiger2: Add test of writing a flattened view
2024-10-07 12:04:33 +02:00
Lofty
13ecbd5c76
quicklogic: test that dividing by a constant does not infer carry chains
2024-10-03 20:05:28 +01:00
Roland Coeurjoly
5ea2c6e6e5
Assume x values for missing signal data in FST
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Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-02 12:08:48 +02:00
Emil J. Tywoniak
997cb30f1f
cxxrtl: test stream operator
2024-10-01 13:25:07 +02:00
Roland Coeurjoly
76c615b2ae
Fix: handle VCD variable references with and without whitespace
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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-01 11:51:20 +02:00
rherveille
ce7db661a8
Added cast to type support ( #4284 )
2024-09-29 17:03:01 -04:00
George Rennie
0572f8806f
opt_reduce: add test for constant $reduce_and/or not being zero width
2024-09-25 16:28:41 +01:00
George Rennie
e105cae4a9
opt_demorgan: add test for zero width cell
2024-09-25 16:10:16 +01:00
Martin Povišer
ea765686b6
aiger2: Adjust hierarchy/port handling
2024-09-18 16:55:02 +02:00
Martin Povišer
6c1fa45995
aiger2: Ingest $pmux
2024-09-18 16:42:56 +02:00
Martin Povišer
d5756eb9be
tests: Add trivial liberty -unit_delay test
2024-09-18 16:17:03 +02:00
Martin Povišer
31476e89b6
tests: Avoid temporary script file
2024-09-18 16:17:03 +02:00
Martin Povišer
8e29675a23
aiger2: Support $bwmux, comparison operators
2024-09-17 13:55:58 +02:00
Martin Povišer
fb26945a20
Start an 'aiger2' backend
2024-09-17 13:55:58 +02:00
Martin Povišer
4cfdb7ab50
Adjust operation naming in aigmap test
2024-09-17 13:55:58 +02:00
