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Code Activity
11199 commits 122 branches 59 tags 72 MiB
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2080 commits

Author SHA1 Message Date
Eddie Hung
e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Marcin Kościelnicki
3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah
edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Miodrag Milanovic
5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Miodrag Milanovic
2897fe4d09 Fix formating 2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a one bit enable signal 2019-08-11 13:59:39 +02:00
Miodrag Milanovic
aa0c37722a fix mixing signals on FF mapping 2019-08-11 11:40:15 +02:00
Miodrag Milanovic
853c755a0c Replaced custom step with setundef 2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38 Fixed data width 2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508 cleanup 2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc 
Add a few comments to document $alu and $lcu
 2019-08-10 09:46:46 +02:00
Eddie Hung
6d254f2de8 Add wreduce to synth_ice40 -dsp as well 2019-08-09 17:05:56 -07:00
Eddie Hung
0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung
041defc5a6 Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Miodrag Milanovic
d51b135e33 Fix CO 2019-08-09 12:37:10 +02:00
Miodrag Milanovic
7a860c5623 Merge remote-tracking branch 'upstream/master' into efinix 2019-08-09 09:46:37 +02:00
Eddie Hung
1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung
2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung
162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung
7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung
57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung
13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
Eddie Hung
dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00
David Shah
0492b8b541 ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:18:59 +01:00
David Shah
cb84ed2326 ecp5: Bring up to date with mul2dsp changes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:14:09 +01:00
David Shah
83b2e02723 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-08 11:40:09 +01:00
David Shah
b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah
f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung
9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00