Martin Povišer
5669724e33
Merge c68fd85b9c into ecf9c9f0cf
2025-04-16 15:03:40 +00:00
Adrien Prost-Boucle
3911a627a8
Clearer diff for the all-x corner case
2025-04-07 07:55:30 +02:00
Adrien Prost-Boucle
7a1729e609
Fix mux xilinx mapping when all inputs are x
2025-04-06 11:43:17 +02:00
Emil J
1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp
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ice40_dsp: fix log_assert issue
2025-03-28 13:32:17 +01:00
YRabbit
c37db637c7
Gowin. Remove unnecessary modules
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Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-03-28 06:34:26 +10:00
Scott Ashcroft
04bbd4e7e2
Make all vector-size related integer params in $print sim model signed
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This fixes iverilog crashes on 32-bit, similar to 95944eb
2025-03-25 13:08:49 +00:00
Miodrag Milanović
733487e730
Merge pull request #4950 from pu-cc/gatemate-serdes-update
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gatemate: Add `CC_SERDES` parameters and update port names
2025-03-20 10:52:23 +01:00
Anhijkt
a9d765e11e
ice40_dsp: group empty wires
2025-03-16 15:11:45 +02:00
Anhijkt
725c489c7e
ice40_dsp: fix log_assert issue
2025-03-15 17:11:32 +02:00
Martin Povišer
6da543a61a
Merge pull request #4818 from povik/macc_v2
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Add `$macc_v2`
2025-03-12 22:55:40 +01:00
KrystalDelusion
bf96ed322d
Merge pull request #4827 from aerkiaga/main
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Update ALU MULT mode in gowin to match nextpnr
2025-03-13 10:49:37 +13:00
Martin Povišer
c68fd85b9c
ql_dsp_simd: Remove array usage failing VS build
2025-03-11 21:57:40 +01:00
Martin Povišer
de61ff848c
quicklogic: Tune include path to fix OOT builds
2025-03-11 21:07:14 +01:00
Martin Povišer
535dab1e19
quicklogic: Fix one more rule
2025-03-11 20:21:54 +01:00
Martin Povišer
79b8ed1b91
quicklogic: Fix missing install rule
2025-03-11 19:39:50 +01:00
Martin Povišer
b6a9d78507
ql_dsp: Add -nocascade
2025-03-11 17:02:36 +01:00
Martin Povišer
4f2a06f55a
quicklogic: Complete DSPv2 flow
2025-03-11 16:37:43 +01:00
Martin Povišer
0d484818a7
ql_dsp_io_regs: Add DSPv2 support, adjust sim model
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Add support for cell type dispatching of the new DSP block; adjust the
definition of MULT and MULTACC variants to support those instances
starting a cascading chain.
2025-03-11 16:35:38 +01:00
Martin Povišer
0180e8f30f
ql_dsp: Fix parameter widths, forbid self-cascading
2025-03-11 16:29:01 +01:00
Martin Povišer
26dc68086f
ql_dsp: Relax packing condition
2025-03-11 16:28:09 +01:00
Martin Povišer
7f833f4c37
ql_dsp: Add help
2025-03-11 16:26:54 +01:00
Martin Povišer
b230c00551
ql_dsp: Fix precondition for cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
f157a868a3
ql_dsp: Add outer loop
2025-03-11 10:35:31 +01:00
Martin Povišer
fde681623c
ql_dsp: Improve cascading detection
2025-03-11 10:35:31 +01:00
Martin Povišer
0615209562
ql_dsp_macc: Support v2 DSP
2025-03-11 10:35:31 +01:00
Martin Povišer
947ca842f9
ql_dsp: Add promotion on cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
c439f8c770
quicklogic: Fix cascading
2025-03-11 10:35:31 +01:00
Martin Povišer
6a3d1cc976
ql_dsp_macc: Avoid ID() macro for common IDs
2025-03-11 10:35:31 +01:00
Martin Povišer
0b8243b742
quicklogic: Revert changes to converge development
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
4cbc92f50f
quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fb3ad314ba
quicklogic: ql_dsp_io_regs debug print
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
15b3ed4747
quicklogic: ql_dsp_macc set fractured mode
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fcdd013c57
quicklogic: allow fractured mode on canonical dspv1 modules
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
62885f1de3
quicklogic: ql_dsp_simd remove unused MODE_BITS packing
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
f55da95ec8
quicklogic: update dspv2_sim.v to v1.1 Feb21
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
ed239b69fd
ql_dsp_macc: whitespace. NFC
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
651d5728d0
ql_dsp_macc: dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
47b270a03e
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-03-11 10:35:30 +01:00
Martin Povišer
e1074e0e4e
qlf_k6n10f: Fix DSPV2 models
2025-03-11 10:35:01 +01:00
Martin Povišer
531374bec1
qlf_k6n10f: New ql_dsp pass, move to DSPV2
2025-03-11 10:35:01 +01:00
Martin Povišer
d8a4991289
Merge pull request #4931 from povik/buf-clean
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opt_clean, simplemap: Add `$buf` handling
2025-03-10 15:10:17 +01:00
Martin Povišer
9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master
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MAX10 updates
2025-03-07 19:59:55 +01:00
Martin Povišer
557047fe1e
opt_clean, simplemap: Add $buf handling
2025-03-07 16:08:38 +01:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
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add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
Krystine Sherwin
0ec5f1b756
pmgen: Move passes out of pmgen folder
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- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
$@))`.
2025-01-31 15:18:28 +13:00
N. Engelhardt
25b400982b
detect aliased I/O ports
2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
