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quicklogic: Revert changes to converge development
This commit is contained in:
Martin Povišer
parent
4cbc92f50f
commit
0b8243b742
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@ -27,11 +27,9 @@ PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
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{
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auto &st = pm.st_ql_dsp_macc;
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log_assert(dsp_version < 3);
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log_assert(dsp_version > 0);
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// Get port widths
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size_t a_width = GetSize(st.mul->getPort(ID(A)));
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@ -51,58 +49,26 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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size_t tgt_b_width;
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size_t tgt_z_width;
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string cell_base_name;
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string cell_base_name = "dsp_t1";
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string cell_size_name = "";
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string cell_cfg_name = "";
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string cell_full_name = "";
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if (dsp_version == 1)
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cell_base_name = "dsp_t1";
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if (dsp_version == 2)
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cell_base_name = "dspv2";
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std::function<void(Cell*)> set_fractured = nullptr;
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auto set_fractured_dspv2 = [](Cell* cell) -> void {cell->setParam(ID(FRAC_MODE), State::S0);};
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if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
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log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width);
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return;
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}
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bool reject = false;
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if (dsp_version == 1) {
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if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
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cell_size_name = "_10x9x32";
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tgt_a_width = 10;
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tgt_b_width = 9;
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tgt_z_width = 19;
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} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
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cell_size_name = "_20x18x64";
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_z_width = 38;
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} else {
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reject = true;
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}
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} else if (dsp_version == 2) {
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if (min_width <= 9 && max_width <= 16 && z_width <= 25) {
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cell_size_name = "_16x9x32";
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tgt_a_width = 16;
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tgt_b_width = 9;
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tgt_z_width = 25;
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} else if (min_width <= 18 && max_width <= 32 && z_width <= 50) {
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cell_size_name = "_32x18x64";
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_z_width = 50;
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set_fractured = set_fractured_dspv2;
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} else {
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reject = true;
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}
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} else if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
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cell_size_name = "_10x9x32";
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tgt_a_width = 10;
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tgt_b_width = 9;
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tgt_z_width = 19;
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} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
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cell_size_name = "_20x18x64";
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_z_width = 38;
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} else {
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log_assert(false);
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}
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if (reject) {
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log_debug("\trejected: too wide (%zd %zd %zd) for v%d\n", min_width, max_width, z_width, dsp_version);
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log_debug("\trejected: too wide (%zd %zd %zd)\n", min_width, max_width, z_width);
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return;
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}
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@ -110,12 +76,15 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type));
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for (auto cell : {st.mul, st.add, st.mux, st.ff})
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if (cell)
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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if (cell)
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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// Add the DSP cell
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RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
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if (cell->type == ID(dsp_t1_20x18x64_cfg_ports))
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cell->setPort(ID(f_mode_i), State::S0);
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// Set attributes
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cell->set_bool_attribute(ID(is_inferred), true);
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@ -135,7 +104,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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cell->setPort(ID(b_i), sig_b);
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// Connect output data port, pad if needed
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if ((size_t)GetSize(sig_z) < tgt_z_width) {
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if ((size_t) GetSize(sig_z) < tgt_z_width) {
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auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
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sig_z.append(wire);
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}
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@ -206,10 +175,6 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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bool subtract = (st.add->type == ID($sub));
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cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
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// Disable fractured mode
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if (set_fractured)
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set_fractured(cell);
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// Mark the cells for removal
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pm.autoremove(st.mul);
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pm.autoremove(st.add);
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@ -235,22 +200,16 @@ struct QlDspMacc : public Pass {
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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{
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int dsp_version = 1;
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log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < a_Args.size(); argidx++) {
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if (a_Args[argidx] == "-dspv2") {
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dsp_version = 2;
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continue;
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}
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break;
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}
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extra_args(a_Args, argidx, a_Design);
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auto l = [dsp_version](ql_dsp_macc_pm &pm) { create_ql_macc_dsp(pm, dsp_version); };
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for (auto module : a_Design->selected_modules())
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(l);
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
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}
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} QlDspMacc;
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