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Merge pull request #5023 from jix/restrict_share_activiation_patterns
share: Restrict activation patterns to potentially relevant signals
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commit
ecf9c9f0cf
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@ -1000,6 +1000,61 @@ struct ShareWorker
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}
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}
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pool<std::pair<SigBit, State>> pattern_bits(const pool<ssc_pair_t> &activation_patterns)
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{
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pool<std::pair<SigBit, State>> bits;
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for (auto const &pattern : activation_patterns) {
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for (int i = 0; i < GetSize(pattern.second); ++i) {
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SigBit bit = pattern.first[i];
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State val = pattern.second[i];
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bits.emplace(bit, val);
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}
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}
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return bits;
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}
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bool onesided_restrict_activation_patterns(
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pool<ssc_pair_t> &activation_patterns, const pool<std::pair<SigBit, State>> &other_bits)
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{
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pool<ssc_pair_t> new_activation_patterns;
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bool simplified = false;
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for (auto const &pattern : activation_patterns) {
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ssc_pair_t new_pair;
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for (int i = 0; i < GetSize(pattern.second); ++i) {
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SigBit bit = pattern.first[i];
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State val = pattern.second[i];
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if (other_bits.count({bit, val == State::S0 ? State::S1 : State::S0})) {
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new_pair.first.append(bit);
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new_pair.second.append(val);
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} else {
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simplified = true;
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}
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}
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new_activation_patterns.emplace(std::move(new_pair));
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}
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activation_patterns = std::move(new_activation_patterns);
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return simplified;
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}
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// Only valid if the patterns on their own (i.e. without considering their input cone) are mutually exclusive!
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bool restrict_activation_patterns(pool<ssc_pair_t> &activation_patterns, pool<ssc_pair_t> &other_activation_patterns)
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{
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pool<std::pair<SigBit, State>> bits = pattern_bits(activation_patterns);
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pool<std::pair<SigBit, State>> other_bits = pattern_bits(other_activation_patterns);
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bool simplified = false;
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simplified |= onesided_restrict_activation_patterns(activation_patterns, other_bits);
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simplified |= onesided_restrict_activation_patterns(other_activation_patterns, bits);
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optimize_activation_patterns(activation_patterns);
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optimize_activation_patterns(other_activation_patterns);
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return simplified;
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}
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RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
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{
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RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
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@ -1299,17 +1354,18 @@ struct ShareWorker
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other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
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all_ctrl_signals.append(p.first);
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}
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int sub1 = qcsat.ez->expression(qcsat.ez->OpOr, cell_active);
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int sub2 = qcsat.ez->expression(qcsat.ez->OpOr, other_cell_active);
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bool pattern_only_solve = qcsat.ez->solve(qcsat.ez->AND(sub1, sub2));
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qcsat.prepare();
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int sub1 = qcsat.ez->expression(qcsat.ez->OpOr, cell_active);
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if (!qcsat.ez->solve(sub1)) {
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log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
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cells_to_remove.insert(cell);
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break;
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}
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int sub2 = qcsat.ez->expression(qcsat.ez->OpOr, other_cell_active);
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if (!qcsat.ez->solve(sub2)) {
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log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
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cells_to_remove.insert(other_cell);
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@ -1317,28 +1373,43 @@ struct ShareWorker
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continue;
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}
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qcsat.ez->non_incremental();
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pool<ssc_pair_t> optimized_cell_activation_patterns = filtered_cell_activation_patterns;
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pool<ssc_pair_t> optimized_other_cell_activation_patterns = filtered_other_cell_activation_patterns;
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all_ctrl_signals.sort_and_unify();
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std::vector<int> sat_model = qcsat.importSig(all_ctrl_signals);
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std::vector<bool> sat_model_values;
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if (pattern_only_solve) {
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qcsat.ez->non_incremental();
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qcsat.ez->assume(qcsat.ez->AND(sub1, sub2));
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all_ctrl_signals.sort_and_unify();
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std::vector<int> sat_model = qcsat.importSig(all_ctrl_signals);
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std::vector<bool> sat_model_values;
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log(" Size of SAT problem: %zu cells, %d variables, %d clauses\n",
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qcsat.imported_cells.size(), qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
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qcsat.ez->assume(qcsat.ez->AND(sub1, sub2));
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if (qcsat.ez->solve(sat_model, sat_model_values)) {
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log(" According to the SAT solver this pair of cells can not be shared.\n");
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log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values));
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for (int i = GetSize(sat_model_values)-1; i >= 0; i--)
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log("%c", sat_model_values[i] ? '1' : '0');
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log("\n");
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continue;
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log(" Size of SAT problem: %zu cells, %d variables, %d clauses\n",
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qcsat.imported_cells.size(), qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
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if (qcsat.ez->solve(sat_model, sat_model_values)) {
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log(" According to the SAT solver this pair of cells can not be shared.\n");
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log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values));
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for (int i = GetSize(sat_model_values)-1; i >= 0; i--)
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log("%c", sat_model_values[i] ? '1' : '0');
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log("\n");
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continue;
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}
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log(" According to the SAT solver this pair of cells can be shared.\n");
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} else {
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log(" According to the SAT solver this pair of cells can be shared. (Pattern only case)\n");
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if (restrict_activation_patterns(optimized_cell_activation_patterns, optimized_other_cell_activation_patterns)) {
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for (auto &p : optimized_cell_activation_patterns)
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log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
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for (auto &p : optimized_other_cell_activation_patterns)
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log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
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}
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}
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log(" According to the SAT solver this pair of cells can be shared.\n");
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if (find_in_input_cone(cell, other_cell)) {
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log(" Sharing not possible: %s is in input cone of %s.\n", log_id(other_cell), log_id(cell));
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continue;
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@ -1354,20 +1425,20 @@ struct ShareWorker
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int cell_select_score = 0;
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int other_cell_select_score = 0;
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for (auto &p : filtered_cell_activation_patterns)
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for (auto &p : optimized_cell_activation_patterns)
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cell_select_score += p.first.size();
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for (auto &p : filtered_other_cell_activation_patterns)
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for (auto &p : optimized_other_cell_activation_patterns)
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other_cell_select_score += p.first.size();
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RTLIL::Cell *supercell;
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pool<RTLIL::Cell*> supercell_aux;
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if (cell_select_score <= other_cell_select_score) {
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RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns, supercell_aux);
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RTLIL::SigSpec act = make_cell_activation_logic(optimized_cell_activation_patterns, supercell_aux);
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supercell = make_supercell(cell, other_cell, act, supercell_aux);
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log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act));
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} else {
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RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns, supercell_aux);
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RTLIL::SigSpec act = make_cell_activation_logic(optimized_other_cell_activation_patterns, supercell_aux);
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supercell = make_supercell(other_cell, cell, act, supercell_aux);
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log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act));
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}
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@ -30,3 +30,26 @@ module test_2(
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end
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endmodule
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module test_3(
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input [3:0] s,
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input [7:0] a, b, c,
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output reg [7:0] y0,
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output reg [7:0] y1,
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output reg [7:0] y2,
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output reg [7:0] y3,
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);
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wire is_onehot = s & (s - 1);
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always @* begin
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y0 <= 0;
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y1 <= 0;
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y2 <= 0;
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y3 <= 0;
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if (s < 3) y0 <= b / c;
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if (3 <= s && s < 6) y1 <= c / b;
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if (6 <= s && s < 9) y2 <= a / b;
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if (9 <= s && s < 12) y3 <= b / a;
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end
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endmodule
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@ -3,11 +3,13 @@ proc;;
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copy test_1 gold_1
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copy test_2 gold_2
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share test_1 test_2;;
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copy test_3 gold_3
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share test_1 test_2 test_3;;
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select -assert-count 1 test_1/t:$mul
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select -assert-count 1 test_2/t:$mul
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select -assert-count 1 test_2/t:$div
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select -assert-count 1 test_3/t:$div
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miter -equiv -flatten -make_outputs -make_outcmp gold_1 test_1 miter_1
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sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1
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@ -15,3 +17,5 @@ sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1
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miter -equiv -flatten -make_outputs -make_outcmp gold_2 test_2 miter_2
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sat -verify -prove trigger 0 -show-inputs -show-outputs miter_2
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miter -equiv -flatten -make_outputs -make_outcmp gold_3 test_3 miter_3
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sat -verify -prove trigger 0 -show-inputs -show-outputs miter_3
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