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ice40_dsp: fix log_assert issue

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Anhijkt 2025-03-15 17:11:32 +02:00
parent 6884c98e08
commit 725c489c7e
1 changed files with 8 additions and 6 deletions
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14
techlibs/ice40/ice40_dsp.pmg
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@ -46,17 +46,19 @@ code sigA sigB sigH
// Only care about those bits that are used
int i;
for (i = 0; i < GetSize(O); i++) {
if (nusers(O[i]) <= 1)
break;
sigH.append(O[i]);
}
for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
;
// This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example
if (i == 0)
reject;
log_assert(nusers(O.extract_end(i)) <= 1);
for (int j = 0; j <= i; j++)
if (nusers(O[j]) == 0)
sigH.append(module->addWire(NEW_ID));
else
sigH.append(O[j]);
endcode
code argQ ffA sigA clock clock_pol