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ice40_dsp: group empty wires
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5ae32efca5
commit
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@ -53,11 +53,16 @@ code sigA sigB sigH
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if (i == 0)
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reject;
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for (int j = 0; j <= i; j++)
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for (int j = 0, wire_width = 0; j <= i; j++)
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if (nusers(O[j]) == 0)
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sigH.append(module->addWire(NEW_ID));
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else
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wire_width++;
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else {
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if (wire_width) { // add empty wires for bit offset if needed
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sigH.append(module->addWire(NEW_ID, wire_width));
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wire_width = 0;
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}
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sigH.append(O[j]);
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}
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endcode
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