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ql_dsp_macc: Support v2 DSP
This commit is contained in:
Martin Povišer
parent
947ca842f9
commit
0615209562
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@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
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static void create_ql_macc_dsp_v1(ql_dsp_macc_pm &pm)
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{
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auto &st = pm.st_ql_dsp_macc;
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@ -82,9 +82,6 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
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// Add the DSP cell
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RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
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if (cell->type == ID(dsp_t1_20x18x64_cfg_ports))
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cell->setPort(ID(f_mode_i), State::S0);
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// Set attributes
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cell->set_bool_attribute(ID(is_inferred), true);
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@ -184,6 +181,151 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
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pm.autoremove(st.ff);
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}
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void create_ql_macc_dsp_v2(ql_dsp_macc_pm &pm)
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{
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auto &st = pm.st_ql_dsp_macc;
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SigSpec sig_a = st.mul->getPort(ID::A);
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SigSpec sig_b = st.mul->getPort(ID::B);
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if (sig_a.size() < sig_b.size())
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std::swap(sig_a, sig_b);
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// Signed / unsigned
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bool ab_signed = st.mul->getParam(ID::A_SIGNED).as_bool();
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log_assert(ab_signed == st.mul->getParam(ID::B_SIGNED).as_bool());
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int z_width = GetSize(st.ff->getPort(ID::Q));
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if (!ab_signed) {
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if (sig_a.msb() != RTLIL::S0 && sig_a.size() < z_width)
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sig_a.append(RTLIL::S0);
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if (sig_b.msb() != RTLIL::S0 && sig_b.size() < z_width)
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sig_b.append(RTLIL::S0);
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}
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int a_width = GetSize(sig_a);
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int b_width = GetSize(sig_b);
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// Determine DSP type or discard if too narrow / wide
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RTLIL::IdString type;
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size_t tgt_a_width;
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size_t tgt_b_width;
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size_t tgt_z_width;
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string cell_base_name = "dspv2";
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string cell_size_name = "";
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string cell_cfg_name = "";
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string cell_full_name = "";
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if (a_width <= 2 && b_width <= 2 && z_width <= 4) {
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log_debug("\trejected: too narrow (%d %d %d)\n", a_width, b_width, z_width);
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return;
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} else if (a_width <= 16 && b_width <= 9 && z_width <= 25) {
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cell_size_name = "_16x9x32";
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tgt_a_width = 16;
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tgt_b_width = 9;
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tgt_z_width = 25; // TODO
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} else if (a_width <= 32 && b_width <= 18 && z_width <= 50) {
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cell_size_name = "_32x18x64";
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tgt_a_width = 32;
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tgt_b_width = 18;
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tgt_z_width = 50;
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} else {
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log_debug("\trejected: too wide (%d %d %d)\n", a_width, b_width, z_width);
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return;
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}
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type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
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log("Inferring MACC %dx%d->%d as %s from:\n", a_width, b_width, z_width, log_id(type));
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for (auto cell : {st.mul, st.add, st.mux, st.ff})
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if (cell)
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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// Add the DSP cell
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RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
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// Set attributes
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cell->set_bool_attribute(ID(is_inferred), true);
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// Get input/output data signals
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SigSpec sig_z;
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sig_z = st.output_registered ? st.ff->getPort(ID::Q) : st.ff->getPort(ID::D);
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// Connect input data ports, sign extend / pad with zeros
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sig_a.extend_u0(tgt_a_width, true);
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sig_b.extend_u0(tgt_b_width, true);
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cell->setPort(ID(a_i), sig_a);
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cell->setPort(ID(b_i), sig_b);
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cell->setPort(ID(c_i), SigSpec(RTLIL::S0, tgt_b_width));
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// Connect output data port, pad if needed
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if ((size_t) GetSize(sig_z) < tgt_z_width) {
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auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
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sig_z.append(wire);
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}
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cell->setPort(ID(z_o), sig_z);
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// Connect clock, reset and enable
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cell->setPort(ID(clock_i), st.ff->getPort(ID::CLK));
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RTLIL::SigSpec rst;
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RTLIL::SigSpec ena;
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if (st.ff->hasPort(ID::ARST)) {
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if (st.ff->getParam(ID::ARST_POLARITY).as_int() != 1) {
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rst = pm.module->Not(NEW_ID, st.ff->getPort(ID::ARST));
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} else {
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rst = st.ff->getPort(ID::ARST);
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}
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} else {
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rst = RTLIL::SigSpec(RTLIL::S0);
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}
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if (st.ff->hasPort(ID::EN)) {
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if (st.ff->getParam(ID::EN_POLARITY).as_int() != 1) {
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ena = pm.module->Not(NEW_ID, st.ff->getPort(ID::EN));
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} else {
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ena = st.ff->getPort(ID::EN);
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}
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} else {
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ena = RTLIL::SigSpec(RTLIL::S1);
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}
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cell->setPort(ID(reset_i), rst);
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cell->setPort(ID(load_acc_i), ena);
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// Insert feedback_i control logic used for clearing / loading the accumulator
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if (st.mux_in_pattern) {
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RTLIL::SigSpec sig_s = st.mux->getPort(ID::S);
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// Depending on the mux port ordering insert inverter if needed
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log_assert(st.mux_ab.in(ID::A, ID::B));
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if (st.mux_ab == ID::A)
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sig_s = pm.module->Not(NEW_ID, sig_s);
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cell->setPort(ID(feedback_i), {RTLIL::S0, RTLIL::S0, sig_s});
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}
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// No acc clear/load
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else {
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cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
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}
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cell->setPort(ID(acc_reset_i), RTLIL::SigSpec(RTLIL::S0));
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// 3 - output post acc; 1 - output pre acc
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cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
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bool subtract = (st.add->type == ID($sub));
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cell->setParam(ID(SUBTRACT), RTLIL::Const(subtract ? RTLIL::S1 : RTLIL::S0));
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// Mark the cells for removal
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pm.autoremove(st.mul);
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pm.autoremove(st.add);
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if (st.mux != nullptr) {
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pm.autoremove(st.mux);
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}
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pm.autoremove(st.ff);
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}
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struct QlDspMacc : public Pass {
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QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {}
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@ -196,20 +338,34 @@ struct QlDspMacc : public Pass {
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log("This pass looks for a multiply-accumulate pattern based on which it infers a\n");
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log("QuickLogic DSP cell.\n");
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log("\n");
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log(" -dspv2\n");
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log(" target DSPv2.\n");
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log("\n");
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}
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
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log_header(design, "Executing QL_DSP_MACC pass.\n");
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bool target_dspv2 = false;
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size_t argidx;
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for (argidx = 1; argidx < a_Args.size(); argidx++) {
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-dspv2") {
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target_dspv2 = true;
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continue;
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}
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break;
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}
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extra_args(a_Args, argidx, a_Design);
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extra_args(args, argidx, design);
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for (auto module : a_Design->selected_modules())
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
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for (auto module : design->selected_modules()) {
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ql_dsp_macc_pm pm(module, module->selected_cells());
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if (target_dspv2)
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pm.run_ql_dsp_macc(create_ql_macc_dsp_v2);
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else
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pm.run_ql_dsp_macc(create_ql_macc_dsp_v1);
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}
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}
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} QlDspMacc;
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