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ql_dsp: Fix parameter widths, forbid self-cascading

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This commit is contained in:
Martin Povišer 2025-03-11 16:29:01 +01:00
parent 26dc68086f
commit 0180e8f30f
1 changed files with 3 additions and 2 deletions
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5
techlibs/quicklogic/ql_dsp.pmg
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@ -50,7 +50,7 @@ code argQ clock_inferred clock reset
clock = dffclock;
reset = dffreset;
log("%s: inferring B path register from flip-flop %s\n", log_id(dsp), log_id(dff));
dsp->parameters[\B_REG] = true;
dsp->parameters[\B_REG] = Const(1, 1);
dsp->setPort(\b_i, dffD);
did_something = true;
}
@ -68,7 +68,7 @@ code argQ clock_inferred clock reset
clock = dffclock;
reset = dffreset;
log("%s: inferring A path register from flip-flop %s\n", log_id(dsp), log_id(dff));
dsp->parameters[\A_REG] = true;
dsp->parameters[\A_REG] = Const(1, 1);
dsp->setPort(\a_i, dffD);
did_something = true;
}
@ -222,6 +222,7 @@ match dsp2
// expect `dsp2` and `add` for exclusive users
filter nusers(port(dsp2, \z_o)) == 2
filter !dsp2->hasPort(\z_cout_o) || nusers(port(dsp2, \z_cout_o)) == 1
filter dsp1 != dsp2
endmatch
match add