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Merge pull request #4942 from Anhijkt/fix-ice40dsp

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ice40_dsp: fix log_assert issue
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Emil J 2025-03-28 13:32:17 +01:00 • committed by GitHub
commit 1b25e1cee0
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2 changed files with 83 additions and 6 deletions
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19
techlibs/ice40/ice40_dsp.pmg
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@ -46,17 +46,24 @@ code sigA sigB sigH
// Only care about those bits that are used
int i;
for (i = 0; i < GetSize(O); i++) {
if (nusers(O[i]) <= 1)
break;
sigH.append(O[i]);
}
for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
;
// This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example
if (i == 0)
reject;
log_assert(nusers(O.extract_end(i)) <= 1);
for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0)
wire_width++;
else {
if (wire_width) { // add empty wires for bit offset if needed
sigH.append(module->addWire(NEW_ID, wire_width));
wire_width = 0;
}
sigH.append(O[j]);
}
endcode
code argQ ffA sigA clock clock_pol