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ql_dsp: Relax packing condition

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This commit is contained in:
Martin Povišer 2025-03-11 16:27:57 +01:00
parent 7f833f4c37
commit 26dc68086f
1 changed files with 2 additions and 4 deletions
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6
techlibs/quicklogic/ql_dsp.pmg
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@ -42,8 +42,7 @@ endcode
// try packing on B input
code argQ clock_inferred clock reset
if ((!dsp->hasPort(\b_cout_o) || nusers(port(dsp, \b_cout_o)) == 1) &&
!param(dsp, \B_REG).as_bool() &&
nusers(port(dsp, \b_i)) == 2) {
!param(dsp, \B_REG).as_bool()) {
argQ = port(dsp, \b_i);
subpattern(in_dffe);
if (dff) {
@ -61,8 +60,7 @@ endcode
// try packing on A input
code argQ clock_inferred clock reset
if ((!dsp->hasPort(\a_cout_o) || nusers(port(dsp, \a_cout_o)) == 1) &&
!param(dsp, \A_REG).as_bool() &&
nusers(port(dsp, \a_i)) == 2) {
!param(dsp, \A_REG).as_bool()) {
argQ = port(dsp, \a_i);
subpattern(in_dffe);
if (dff) {