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Code Activity
16027 commits 121 branches 59 tags 69 MiB
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2203 commits

Author SHA1 Message Date
Eddie Hung
c6fd057eda Add abc9.v testcase to simple_abc9 2019-02-21 10:37:45 -08:00
Eddie Hung
be061810d7 Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig 2019-02-21 09:31:17 -08:00
Eddie Hung
8e789da74c Revert "Add -B option to autotest.sh to append to backend_opts" 
This reverts commit 281f2aadca.
 2019-02-21 09:22:29 -08:00
Eddie Hung
869343b040 simple_abc9 tests to now preserve memories 2019-02-20 16:19:01 -08:00
Eddie Hung
4035ec8933 Remove simple_defparam tests 2019-02-20 15:45:45 -08:00
Eddie Hung
43d5471570 Move tests/techmap/abc9 to simple_abc9 2019-02-20 15:34:59 -08:00
Eddie Hung
945bbcc298 Add tests/simple_abc9 2019-02-20 15:31:35 -08:00
Eddie Hung
ef1a1402bc Add a quick abc9 test 2019-02-19 15:25:03 -08:00
Jim Lawson
5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Eddie Hung
f9af902532 Merge branch 'master' into xaig 2019-02-19 14:20:04 -08:00
Eddie Hung
430a7548bc One more merge conflict 2019-02-17 11:50:55 -08:00
Eddie Hung
17cd5f759f Merge https://github.com/YosysHQ/yosys into dff_init 2019-02-17 11:49:06 -08:00
Eddie Hung
03a533d102 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-02-17 11:44:01 -08:00
Jim Lawson
34153adef4 Append (instead of over-writing) EXTRA_FLAGS 2019-02-15 11:56:51 -08:00
Jim Lawson
fc1c9aa11f Update cells supported for verilog to FIRRTL conversion. 
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
 2019-02-15 11:14:17 -08:00
Eddie Hung
587872236e Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
Eddie Hung
4e6c5e4672 Add binary AIGs converted from AAG 2019-02-08 11:41:25 -08:00
Eddie Hung
4167b15de5 Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig 2019-02-06 14:31:11 -08:00
Eddie Hung
3f87cf86cc Revert most of autotest.sh; for non *.v use Yosys to translate 2019-02-06 14:30:19 -08:00
Eddie Hung
115883f467 Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
Eddie Hung
281f2aadca Add -B option to autotest.sh to append to backend_opts 2019-02-06 14:14:55 -08:00
Eddie Hung
03cf1532a7 Extend testcase 2019-02-06 14:02:11 -08:00
Eddie Hung
a9674bd2ec Add testcase 2019-02-06 12:49:30 -08:00
Eddie Hung
fdd55d064b Rename ASCII tests 2019-02-06 12:20:36 -08:00
Eddie Hung
3f0bb441f8 Add tests 2019-02-04 16:46:24 -08:00
Clifford Wolf
9666cca9dd Remove asicworld tests for (unsupported) switch-level modelling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-27 09:17:02 +01:00
Clifford Wolf
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark
bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
whitequark
a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark
4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
whitequark
42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Larry Doolittle
99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt 
equiv_opt: new command, for verifying optimization passes
 2018-12-16 15:54:26 +01:00
whitequark
7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping. 
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
 2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65 equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
Clifford Wolf
7d1088afc4 Add missing .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:37 +01:00
whitequark
9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
whitequark
45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
Ruben Undheim
458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Udi Finkelstein
106af19b69 Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00