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whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
..
asicworld Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
bram Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
hana Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
lut equiv_opt: new command, for verifying optimization passes. 2018-12-07 17:20:34 +00:00
memories Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
opt opt_expr: improve simplification of comparisons with large constants. 2019-01-02 15:45:28 +00:00
realmath Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
sat Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
share Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
simple Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
smv Progress in SMV back-end 2015-06-19 14:08:46 +02:00
sva Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
svinterfaces Add missing .gitignore 2018-12-06 07:29:37 +01:00
techmap Added read-enable to memory model 2015-09-25 12:23:11 +02:00
tools Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various Modified errors into warnings 2018-06-05 18:03:22 +03:00
vloghtb bugfix in blif front-end 2015-05-18 11:15:49 +02:00