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Squelch a little more trailing whitespace

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Larry Doolittle 2018-12-28 08:24:31 -08:00 • committed by Clifford Wolf
parent 245724a504
commit 99706b3bf4
2 changed files with 4 additions and 4 deletions
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tests/sva/basic01.sv
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@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
write <= ctrl;
ready <= write;
end
a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL
a_wr: assert property ( @(posedge clock) write |-> ready );