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Merge pull request #724 from whitequark/equiv_opt

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equiv_opt: new command, for verifying optimization passes
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Clifford Wolf 2018-12-16 15:54:26 +01:00 • committed by GitHub
commit 2a681909df
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6 changed files with 173 additions and 27 deletions
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13
tests/lut/check_map.ys
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@ -1,13 +1,4 @@
design -save preopt
simplemap
techmap -map +/gate2lut.v -D LUT_WIDTH=4
equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
design -load postopt
select -assert-count 1 t:$lut
design -stash postopt
design -copy-from preopt -as preopt top
design -copy-from postopt -as postopt top
equiv_make preopt postopt equiv
prep -flatten -top equiv
equiv_induct
equiv_status -assert

3
tests/opt/ice40_carry.v
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@ -1,3 +0,0 @@
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

13
tests/opt/opt_lut.ys
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@ -1,15 +1,4 @@
read_verilog opt_lut.v
synth_ice40
ice40_unlut
design -save preopt
opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
design -stash postopt
design -copy-from preopt -as preopt top
design -copy-from postopt -as postopt top
equiv_make preopt postopt equiv
techmap -map ice40_carry.v
prep -flatten -top equiv
equiv_induct
equiv_status -assert
equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3