Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

tests/errors/syntax_err01.v

@@ -0,0 +1,4 @@
+module a;
+integer [31:0]w;
+endmodule
+

tests/errors/syntax_err02.v

@@ -0,0 +1,7 @@
+module a;
+task to (
+  input integer [3:0]x
+);
+endtask
+endmodule
+

tests/errors/syntax_err03.v

@@ -0,0 +1,7 @@
+module a;
+task to (
+  input [3]x
+);
+endtask
+endmodule
+

tests/errors/syntax_err04.v

@@ -0,0 +1,4 @@
+module a;
+wire [3]x;
+endmodule
+

tests/errors/syntax_err05.v

@@ -0,0 +1,4 @@
+module a;
+input x[2:0];
+endmodule
+

tests/errors/syntax_err06.v

@@ -0,0 +1,6 @@
+module a;
+initial
+begin : label1
+end: label2
+endmodule
+

tests/errors/syntax_err07.v

@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = (4)55;
+endmodule
+

tests/errors/syntax_err08.v

@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = x 55;
+endmodule
+

tests/errors/syntax_err09.v

@@ -0,0 +1,3 @@
+module a(input wire x = 1'b0);
+endmodule
+

tests/errors/syntax_err10.v

@@ -0,0 +1,3 @@
+module a;
+parameter integer [2:0]x=0;
+endmodule

tests/errors/syntax_err11.v

@@ -0,0 +1,3 @@
+module a;
+parameter integer real x=0;
+endmodule

tests/errors/syntax_err12.v

@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule

tests/errors/syntax_err13.v

@@ -0,0 +1,4 @@
+module a #(p = 0)
+();
+endmodule
+