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equiv_opt: pass -D EQUIV when techmapping.

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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
This commit is contained in:
whitequark 2018-12-07 16:58:33 +00:00
parent c38ea9ae65
commit 7ff5a9db2d
4 changed files with 7 additions and 6 deletions
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3
tests/opt/ice40_carry.v
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@ -1,3 +0,0 @@
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

2
tests/opt/opt_lut.ys
View file

@ -1,4 +1,4 @@
read_verilog opt_lut.v
synth_ice40
ice40_unlut
equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3