mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Merge pull request #770 from whitequark/opt_expr_cmp

Browse source 
opt_expr: refactor and improve simplification of comparisons
This commit is contained in:
Clifford Wolf 2019-01-02 17:34:04 +01:00 • committed by GitHub
commit 0fc6e2bfcf
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 182 additions and 101 deletions
Download patch file Download diff file Expand all files Collapse all files

40
tests/opt/opt_expr_cmp.v Normal file
View file

@ -0,0 +1,40 @@
module top(...);
input [3:0] a;
output o1_1 = 4'b0000 > a;
output o1_2 = 4'b0000 <= a;
output o1_3 = 4'b1111 < a;
output o1_4 = 4'b1111 >= a;
output o1_5 = a < 4'b0000;
output o1_6 = a >= 4'b0000;
output o1_7 = a > 4'b1111;
output o1_8 = a <= 4'b1111;
output o2_1 = 4'sb0000 > $signed(a);
output o2_2 = 4'sb0000 <= $signed(a);
output o2_3 = $signed(a) < 4'sb0000;
output o2_4 = $signed(a) >= 4'sb0000;
output o3_1 = 4'b0100 > a;
output o3_2 = 4'b0100 <= a;
output o3_3 = a < 4'b0100;
output o3_4 = a >= 4'b0100;
output o4_1 = 5'b10000 > a;
output o4_2 = 5'b10000 >= a;
output o4_3 = 5'b10000 < a;
output o4_4 = 5'b10000 <= a;
output o4_5 = a < 5'b10000;
output o4_6 = a <= 5'b10000;
output o4_7 = a > 5'b10000;
output o4_8 = a >= 5'b10000;
output o5_1 = 5'b10100 > a;
output o5_2 = 5'b10100 >= a;
output o5_3 = 5'b10100 < a;
output o5_4 = 5'b10100 <= a;
output o5_5 = a < 5'b10100;
output o5_6 = a <= 5'b10100;
output o5_7 = a > 5'b10100;
output o5_8 = a >= 5'b10100;
endmodule

4
tests/opt/opt_expr_cmp.ys Normal file
View file

@ -0,0 +1,4 @@
read_verilog opt_expr_cmp.v
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 0 t:$gt t:$ge t:$lt t:$le