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Support for 'modports' for System Verilog interfaces

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This commit is contained in:
Ruben Undheim 2018-10-12 20:58:37 +02:00
parent 75009ada3c
commit 458a94059e
8 changed files with 121 additions and 14 deletions
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20
tests/simple/svinterface1.sv
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@ -19,7 +19,7 @@ module TopModule(
assign MyInterfaceInstance.setting = 1;
assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
// assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
endmodule
@ -32,13 +32,25 @@ interface MyInterface #(
logic [1:0] mysig_out;
modport submodule1 (
input setting,
output other_setting,
output mysig_out
);
modport submodule2 (
input setting,
output other_setting,
input mysig_out
);
endinterface
module SubModule1(
input logic clk,
input logic rst,
MyInterface u_MyInterface,
MyInterface.submodule1 u_MyInterface,
input logic [1:0] sig
);
@ -68,9 +80,11 @@ module SubModule2(
input logic clk,
input logic rst,
MyInterface u_MyInterfaceInSub2,
MyInterface.submodule2 u_MyInterfaceInSub2,
input logic [1:0] sig
);
assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
endmodule