mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-10 08:01:14 +00:00
Code Activity
17741 commits 138 branches 70 tags 85 MiB
Commit graph

17741 commits

This branch
This branch
All branches
Author SHA1 Message Date
Emil J. Tywoniak
32d013f807 extract: leave signorm mode 2026-07-22 01:29:55 +02:00
Emil J. Tywoniak
14e6c2ee3a signorm: an unconnected output port does not claim a driver 2026-07-22 01:29:06 +02:00
Emil J. Tywoniak
ade8932468 rtlil: register a cloned cell's ports with the signorm index 2026-07-22 01:28:57 +02:00
Emil J. Tywoniak
a8cec7da30 rtlil: resolve positional cell ports before giving up on a direction 2026-07-22 01:28:34 +02:00
Emil J. Tywoniak
8db06bb819 mul2dsp: declare $__mul and $__soft_mul so their ports have directions 2026-07-22 01:28:24 +02:00
Emil J. Tywoniak
6c464a2191 sigNormalize: turn $connect cells back into connections on the way out 2026-07-22 01:28:09 +02:00
Emil J. Tywoniak
33a6cac8b9 opt_dff: keep the signorm index alive across the pass 2026-07-22 01:27:51 +02:00
Emil J. Tywoniak
75fc5753a4 tests: exclude signorm marker cells from two more cell-count assertions 2026-07-22 01:27:00 +02:00
Emil J. Tywoniak
9e2c65388f timeest: leave signorm mode 2026-07-22 01:27:00 +02:00
Emil J. Tywoniak
8e530b82d8 ffinit: an x init bit is the absence of a value, not a conflict 2026-07-22 01:26:52 +02:00
Emil J. Tywoniak
ab12fb313b ice40_opt: retire the wrapper's ports before reinterpreting it as $lut 2026-07-22 01:26:33 +02:00
Emil J. Tywoniak
baa8e18964 opt_clean: trace $connect edges from the liveness roots too 2026-07-22 01:26:23 +02:00
Emil J. Tywoniak
5c7f7d4a3d WIP opt_clean: garbage collect against the signorm index 2026-07-22 01:25:39 +02:00
Emil J. Tywoniak
ed7e50be24 tests: exclude signorm marker cells from cell-count assertions 2026-07-22 01:22:17 +02:00
Emil J. Tywoniak
e27e695c9e passes: leave signorm mode where the index cannot be maintained 2026-07-22 01:22:01 +02:00
Emil J. Tywoniak
46603f72b3 memory_libmap: provide blackboxes for the RAM cells it instantiates 2026-07-22 01:21:43 +02:00
Emil J. Tywoniak
d80ad67f64 check: ask per module whether it carries a signorm index 2026-07-22 01:21:18 +02:00
Emil J. Tywoniak
82e6b8995b memory_bram: intern generated blackbox names as public twines 2026-07-22 01:21:00 +02:00
Emil J. Tywoniak
3d45ce0fbc sigmap: take the signorm index's map directly instead of via connections() 2026-07-22 01:21:00 +02:00
Emil J. Tywoniak
c17cf30775 opt_dff: only build the ModWalker index under -sat 2026-07-22 01:20:33 +02:00
Emil J. Tywoniak
024a71626d opt_expr: sub_not signorm compatibility 
Route the (2^k-1)-x -> ~x rewrite through OptExprPatcher like its
sibling transforms in this file, instead of raw module->Not +
module->connect + module->remove. Loosen the postopt assertion to
tolerate the $input_port shim cell bufnorm adds for the (still
signorm-active) input port, matching the t:$*_port %d idiom already
used by opt_expr_alu.ys and other sibling tests.
 2026-07-20 16:40:46 +02:00
Emil J. Tywoniak
71e2045e38 proc_mux: WIP 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
a7938567fe rtlil: sort twines by string, not by ID, in sort methods 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
2999f9de60 ff: fix src_twine 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
56b61efeda json: fix twine escaping 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
5a0a978938 rtlil_backend: fix dumping sigsig connections 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
8b47d41835 sort: fix whitespace 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
5f437ab076 write_verilog: write out src twines as src attributes 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
6b6847af51 tests/gatemate: update fsm LUT counts for new proc src mapping 
CC_LUT2 1 (was 2), CC_L2T4 max 15 (was 14) reflect the cell mapping
produced after the proc src-location changes.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
d72d4c8bba techmap: decode derived_name in the map pool, not the target design 
derived_name and the template's marker wire are interned in map->twines;
decoding them with design->twines read an out-of-range/foreign pool slot
(garbage, or a crash once pool sizes diverge) in the _TECHMAP_FAIL_ log.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
e41ea6788e genrtlil: intern action src as verbatim Twine 
add(std::string) tags bare strings as public names, so a single-source
concat (which returns the lone ref unchanged) decoded with a spurious
'\' prefix, splitting one source file into two in linecoverage output.
add(Twine{}) stores the location string verbatim like set_src_attr.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
7f791a4fb9 proc_dff: better error context 
(cherry picked from commit 404ce980e4)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
cf3867bb14 proc_mux: include switch expression location in $eq src 
(cherry picked from commit 383daa1eb3)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
3d2e268154 kernel: add SwitchRule signal_src 
(cherry picked from commit 53585db9f7)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
4f9fa58efa docs: workaround for warning from dump 
(cherry picked from commit 85a17b0366)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
c74bc43cfd proc_mux, genrtlil: make use of case_src for better case condition vs block tracking 
(cherry picked from commit a24c260998)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
b2d57e5d41 rtlil: add case_src to CaseRule 
(cherry picked from commit a217a5c716)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
9bc771e051 proc_mux: copy switch src to _CMP wire 
(cherry picked from commit 502ba3734b)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
6182c7dd85 proc_mux: copy mux src to Y port 
(cherry picked from commit da65a18f39)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
e455564b6e proc_mux: add comments 
(cherry picked from commit ee800087e8)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
cf857b6154 proc_mux: optimize source map locality for index density 
(cherry picked from commit b3aea1b5d2)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
ea60c06c43 proc_dff: add wire src attributes to dff cells 
(cherry picked from commit 4072bcfd0b)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
0aaf46c692 verific: use SyncActions 
(cherry picked from commit f4a69805ae)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
a566acd802 proc_mux: default to case src when action src is missing 
(cherry picked from commit 469083dcaa)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
707bac5208 proc_mux: add src test 
(cherry picked from commit a2e8e352b6)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
90324ad24f docs: word_mux grammar 
(cherry picked from commit 985e98935f)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
a606d6416d proc_mux: refactor 
(cherry picked from commit 778a667a91)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
f6844f0e36 proc_mux: emit fused action location src attributes on procmuxes 
(cherry picked from commit cacd584347)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
6f3b384ac4 rtlil: add source tracking to CaseRule actions 
(cherry picked from commit c36370f227)
 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
9ac4905aeb verilog: fix case location 
(cherry picked from commit 7713b5a811)
 2026-07-20 15:01:30 +02:00