mirror of
https://github.com/YosysHQ/yosys
synced 2026-08-14 09:55:37 +00:00
memory_bram: intern generated blackbox names as public twines
This commit is contained in:
parent
3d45ce0fbc
commit
82e6b8995b
1 changed files with 3 additions and 3 deletions
|
|
@ -157,19 +157,19 @@ struct rules_t
|
|||
}
|
||||
|
||||
log_debug("setting up %s\n", name);
|
||||
Module* mod = design->addModule(design->twines.add(Twine{name.str()}));
|
||||
Module* mod = design->addModule(design->twines.add(std::string{name.str()}));
|
||||
mod->set_bool_attribute(ID::blackbox);
|
||||
|
||||
for (auto [name, width] : inputs)
|
||||
{
|
||||
log_debug("input %s width %d\n", name.c_str(), width);
|
||||
mod->addWire(design->twines.add(Twine{name.str()}), width)->port_input = true;
|
||||
mod->addWire(design->twines.add(std::string{name.str()}), width)->port_input = true;
|
||||
}
|
||||
|
||||
for (auto [name, width] : outputs)
|
||||
{
|
||||
log_debug("output %s width %d\n", name.c_str(), width);
|
||||
mod->addWire(design->twines.add(Twine{name.str()}), width)->port_output = true;
|
||||
mod->addWire(design->twines.add(std::string{name.str()}), width)->port_output = true;
|
||||
}
|
||||
|
||||
mod->fixup_ports();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue